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Searched refs:RecVec (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp272 const RecVec Defs = in checkSTIPredicates()
622 RecVec SWDefs, SRDefs; in collectSchedRW()
768 RecVec &WriteDefs, RecVec &ReadDefs) { in splitSchedReadWrites()
782 RecVec WriteDefs; in findRWs()
783 RecVec ReadDefs; in findRWs()
1293 const RecVec *InstDefs = Sets.expand(Rec); in inferFromInstRWs()
1675 static void dumpRecVec(const RecVec &RV) { in dumpRecVec()
1721 RecVec Preds; in inferFromTransitions()
1833 RecVec CheckUnits = in verifyProcResourceGroups()
1838 RecVec OtherUnits = in verifyProcResourceGroups()
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H A DCodeGenSchedule.h36 using RecVec = std::vector<Record*>; variable
59 RecVec Aliases;
103 RecVec PredTerm;
146 RecVec InstRWs;
231 RecVec ItinDefList;
235 RecVec ItinRWDefs;
242 RecVec WriteResDefs;
243 RecVec ReadAdvanceDefs;
246 RecVec ProcResourceDefs;
441 RecVec ProcResourceDefs;
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H A DPredicateExpander.h55 using RecVec = std::vector<Record *>; variable
76 void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
77 void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
78 void expandPredicateSequence(raw_ostream &OS, const RecVec &Sequence,
94 void expandOpcodeSwitchStatement(raw_ostream &OS, const RecVec &Cases,
H A DSubtargetEmitter.cpp191 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList, in printFeatureMask()
280 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
347 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
360 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
406 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
438 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
452 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
678 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResourceSubUnits()
838 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
981 RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles, in ExpandProcResources()
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H A DPredicateExpander.cpp143 const RecVec &Opcodes) { in expandCheckOpcode()
173 const RecVec &Opcodes) { in expandCheckPseudo()
181 const RecVec &Sequence, in expandPredicateSequence()
271 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes"); in expandOpcodeSwitchCase()
285 const RecVec &Cases, in expandOpcodeSwitchStatement()
465 RecVec Delegates = Fn.getDeclaration()->getValueAsListOfDefs("Delegates"); in expandPrologue()
H A DDFAPacketizerEmitter.cpp83 void createScheduleClasses(unsigned ItineraryIdx, const RecVec &Itineraries);
192 const RecVec &Itineraries) { in createScheduleClasses()
H A DInstrInfoEmitter.cpp675 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitMCIIHelperMethods()
895 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitTIIHelperMethods()
H A DRegisterInfoEmitter.cpp1679 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
H A DCodeGenRegisters.cpp756 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/TableGen/
H A DSetTheory.h67 using RecVec = std::vector<Record *>;
98 using ExpandMap = std::map<Record *, RecVec>;
140 const RecVec *expand(Record *Set);
/freebsd-14.2/contrib/llvm-project/llvm/lib/TableGen/
H A DSetTheory.cpp35 using RecVec = SetTheory::RecVec; typedef
229 if (const RecVec *Result = ST.expand(Rec)) in apply()
284 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
307 const RecVec *SetTheory::expand(Record *Set) { in expand()
322 RecVec &EltVec = Expansions[Set]; in expand()