258   const RecVec Decls = Records.getAllDerivedDefinitions("STIPredicateDecl");  in checkSTIPredicates()
272   const RecVec Defs =  in checkSTIPredicates()
275     RecVec Opcodes = R->getValueAsListOfDefs("Opcodes");  in checkSTIPredicates()
316     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
322       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
347     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
354       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
422   RecVec RV = Records.getAllDerivedDefinitions("STIPredicate");  in collectSTIPredicates()
458   RecVec MCPredicates = Records.getAllDerivedDefinitions("TIIPredicate");  in checkMCInstPredicates()
480   RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit");  in collectRetireControlUnits()
495   RecVec Queues = Records.getAllDerivedDefinitions("MemoryQueue");  in collectLoadStoreQueueInfo()
539   RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");  in collectProcModels()
589 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,  in scanSchedRW()
596     RecVec Seq = RWDef->getValueAsListOfDefs("Writes");  in scanSchedRW()
602     RecVec Vars = RWDef->getValueAsListOfDefs("Variants");  in scanSchedRW()
605       RecVec Selected = Variant->getValueAsListOfDefs("Selected");  in scanSchedRW()
622   RecVec SWDefs, SRDefs;  in collectSchedRW()
627     RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");  in collectSchedRW()
638   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedRW()
641     RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
652   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectSchedRW()
655     RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
667   RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");  in collectSchedRW()
724       } RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");  in collectSchedRW()
757     const RecVec &RADefs = ProcModel.ReadAdvanceDefs;  in hasReadOfWrite()
759       RecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");  in hasReadOfWrite()
767 static void splitSchedReadWrites(const RecVec &RWDefs,  in splitSchedReadWrites()
768                                  RecVec &WriteDefs, RecVec &ReadDefs) {  in splitSchedReadWrites()
780 void CodeGenSchedModels::findRWs(const RecVec &RWDefs,  in findRWs()
782   RecVec WriteDefs;  in findRWs()
783   RecVec ReadDefs;  in findRWs()
790 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,  in findRWs()
908   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedClasses()
956     const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;  in collectSchedClasses()
1014 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {  in createSchedClassName()
1071   const RecVec *InstDefs = Sets.expand(InstRWDef);  in createInstRWClass()
1090       const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;  in createInstRWClass()
1092         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);  in createInstRWClass()
1178     RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");  in collectProcItins()
1218   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectProcItinRW()
1273       RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");  in inferFromItinClass()
1293     const RecVec *InstDefs = Sets.expand(Rec);  in inferFromInstRWs()
1397     RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in mutuallyExclusive()
1463       const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1495       const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1545     RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");  in pushVariant()
1675 static void dumpRecVec(const RecVec &RV) {  in dumpRecVec()
1684                            const RecVec &Preds) {  in dumpTransition()
1721     RecVec Preds;  in inferFromTransitions()
1811 bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {  in hasSuperGroup()
1815     RecVec SuperUnits = ProcResourceDef->getValueAsListOfDefs("Resources");  in hasSuperGroup()
1833     RecVec CheckUnits =  in verifyProcResourceGroups()
1838       RecVec OtherUnits =  in verifyProcResourceGroups()
1858   RecVec RegisterFileDefs = Records.getAllDerivedDefinitions("RegisterFile");  in collectRegisterFiles()
1880     RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");  in collectRegisterFiles()
1925   RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");  in collectProcResources()
1930   RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");  in collectProcResources()
1935   RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");  in collectProcResources()
1940   RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");  in collectProcResources()
1949   RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");  in collectProcResources()
2029       const RecVec &InstRWs = SC.InstRWs;  in checkCompleteness()
2062       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");  in collectItinProcResources()
2186   RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;  in addWriteRes()
2192   RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");  in addWriteRes()
2201   RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;  in addReadAdvance()