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Searched refs:RB_CTRL (Results 1 – 2 of 2) sorted by relevance

/freebsd-14.2/sys/dev/msk/
H A Dif_msk.c3949 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); in msk_init_locked()
4066 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); in msk_set_rambuffer()
4086 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); in msk_set_rambuffer()
4087 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); in msk_set_rambuffer()
4090 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); in msk_set_rambuffer()
4100 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); in msk_set_rambuffer()
4101 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); in msk_set_rambuffer()
4102 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); in msk_set_rambuffer()
4184 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), in msk_stop()
4204 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); in msk_stop()
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H A Dif_mskreg.h617 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ macro