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Searched refs:OrigMI (Results 1 – 9 of 9) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp214 auto OrigOp = OrigMI.getOpcode(); in createDPPInst()
234 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI, in createDPPInst()
236 .setMIFlags(OrigMI.getFlags()); in createDPPInst()
377 if (Mod0 && TII->isVOP3(OrigMI) && !TII->isVOP3P(OrigMI)) in createDPPInst()
631 auto &OrigMI = *Use->getParent(); in combineDPPMov() local
634 auto OrigOp = OrigMI.getOpcode(); in combineDPPMov()
666 bool IsShrinkable = isShrinkable(OrigMI); in combineDPPMov()
695 << " " << OrigMI in combineDPPMov()
709 auto *BB = OrigMI.getParent(); in combineDPPMov()
711 BB->insert(OrigMI, NewMI); in combineDPPMov()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp106 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI, in allUsesAvailableAt() argument
111 for (const MachineOperand &MO : OrigMI->operands()) { in allUsesAvailableAt()
168 assert(RM.OrigMI && "No defining instruction for remattable value"); in canRematerializeAt()
169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
172 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI)) in canRematerializeAt()
176 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
188 assert(RM.OrigMI && "Invalid remat"); in rematerializeAt()
189 TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri); in rematerializeAt()
H A DInlineSpiller.cpp649 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); in reMaterializeFor()
667 if (RM.OrigMI->canFoldAsLoad() && in reMaterializeFor()
668 foldMemoryOperand(Ops, RM.OrigMI)) { in reMaterializeFor()
H A DModuloSchedule.cpp1158 MachineInstr *OrigMI = OrigInstr->second; in rewriteScheduledInstr() local
1159 int StageSched = Schedule.getStage(OrigMI); in rewriteScheduledInstr()
1160 int CycleSched = Schedule.getCycle(OrigMI); in rewriteScheduledInstr()
1168 (CyclePhi <= CycleSched || OrigMI->isPHI())) in rewriteScheduledInstr()
H A DSplitKit.cpp612 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); in defFromParent()
H A DRegisterCoalescer.cpp1365 RM.OrigMI = DefMI; in reMaterializeTrivialDef()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp85 Register getSuperRegDestIfDead(MachineInstr *OrigMI) const;
190 Register FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI) const { in getSuperRegDestIfDead()
192 Register OrigDestReg = OrigMI->getOperand(0).getReg(); in getSuperRegDestIfDead()
251 unsigned Opc = OrigMI->getOpcode(); (void)Opc; in getSuperRegDestIfDead()
260 for (auto &MO: OrigMI->implicit_operands()) { in getSuperRegDestIfDead()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h190 MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains member
198 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp108 static bool hasAllNBitUsers(const MachineInstr &OrigMI, in hasAllNBitUsers() argument
115 Worklist.push_back(std::make_pair(&OrigMI, OrigBits)); in hasAllNBitUsers()
333 static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, in hasAllWUsers() argument
335 return hasAllNBitUsers(OrigMI, ST, MRI, 32); in hasAllWUsers()