Lines Matching refs:OrigMI
63 MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
68 MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
204 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, in createDPPInst() argument
214 auto OrigOp = OrigMI.getOpcode(); in createDPPInst()
234 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI, in createDPPInst()
235 OrigMI.getDebugLoc(), TII->get(DPPOp)) in createDPPInst()
236 .setMIFlags(OrigMI.getFlags()); in createDPPInst()
241 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
245 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
277 auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers); in createDPPInst()
301 auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers); in createDPPInst()
313 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
334 auto *Mod2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers); in createDPPInst()
343 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst()
356 auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp); in createDPPInst()
360 auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in); in createDPPInst()
365 auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod); in createDPPInst()
372 TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) { in createDPPInst()
377 if (Mod0 && TII->isVOP3(OrigMI) && !TII->isVOP3P(OrigMI)) in createDPPInst()
389 TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) { in createDPPInst()
406 auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo); in createDPPInst()
410 auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi); in createDPPInst()
482 MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR, in createDPPInst() argument
486 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
491 if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) { in createDPPInst()
503 return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable); in createDPPInst()
631 auto &OrigMI = *Use->getParent(); in combineDPPMov() local
632 LLVM_DEBUG(dbgs() << " try: " << OrigMI); in combineDPPMov()
634 auto OrigOp = OrigMI.getOpcode(); in combineDPPMov()
638 Register FwdReg = OrigMI.getOperand(0).getReg(); in combineDPPMov()
641 if (execMayBeModifiedBeforeAnyUse(*MRI, FwdReg, OrigMI)) { in combineDPPMov()
647 unsigned OpNo, E = OrigMI.getNumOperands(); in combineDPPMov()
649 if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) { in combineDPPMov()
650 FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm(); in combineDPPMov()
662 RegSeqWithOpNos[&OrigMI].push_back(OpNo); in combineDPPMov()
666 bool IsShrinkable = isShrinkable(OrigMI); in combineDPPMov()
675 if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) { in combineDPPMov()
680 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov()
681 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in combineDPPMov()
682 if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1] in combineDPPMov()
687 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov()
695 << " " << OrigMI in combineDPPMov()
700 LLVM_DEBUG(dbgs() << " combining: " << OrigMI); in combineDPPMov()
702 if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR, in combineDPPMov()
708 assert(Use == Src1 && OrigMI.isCommutable()); // by check [1] in combineDPPMov()
709 auto *BB = OrigMI.getParent(); in combineDPPMov()
710 auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI); in combineDPPMov()
711 BB->insert(OrigMI, NewMI); in combineDPPMov()
726 OrigMIs.push_back(&OrigMI); in combineDPPMov()