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Searched refs:OpReg (Results 1 – 17 of 17) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp192 const MCAOperand *OpReg = Inst.getOperand(0); in computeWaitCnt() local
194 assert(OpReg && OpReg->isReg() && "First operand should be a register."); in computeWaitCnt()
196 if (OpReg->getReg() != AMDGPU::SGPR_NULL) { in computeWaitCnt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1736 .addReg(OpReg).addImm(1); in X86SelectBranch()
1768 if (OpReg == 0) return false; in X86SelectBranch()
1772 unsigned KOpReg = OpReg; in X86SelectBranch()
1777 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, X86::sub_8bit); in X86SelectBranch()
1780 .addReg(OpReg) in X86SelectBranch()
1789 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
2361 if (OpReg == 0) in X86SelectSelect()
2367 .addReg(OpReg); in X86SelectSelect()
2406 if (OpReg == 0) in X86SelectIntToFP()
2460 if (OpReg == 0) in X86SelectFPExtOrFPTrunc()
[all …]
H A DX86SpeculativeLoadHardening.cpp1649 Register OpReg = Op->getReg(); in hardenLoadAddr() local
1650 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr()
1688 .addReg(OpReg); in hardenLoadAddr()
1719 .addReg(OpReg); in hardenLoadAddr()
1732 .addReg(OpReg); in hardenLoadAddr()
1741 .addReg(OpReg) in hardenLoadAddr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp297 Register OpReg = MO.getReg(); in optimizeSDPattern() local
299 if (!OpReg.isVirtual()) in optimizeSDPattern()
302 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
H A DARMInstructionSelector.cpp1043 Register OpReg = I.getOperand(2).getReg(); in select() local
1044 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
H A DARMFastISel.cpp1263 Register OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1267 .addReg(OpReg).addImm(1)); in SelectBranch()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp2830 Register OpReg = Op.getReg(); in fixVALUMaskWriteHazard() local
2835 if (OpReg == AMDGPU::EXEC || in fixVALUMaskWriteHazard()
2836 OpReg == AMDGPU::EXEC_LO || in fixVALUMaskWriteHazard()
2837 OpReg == AMDGPU::EXEC_HI) in fixVALUMaskWriteHazard()
2841 if (OpReg == AMDGPU::VCC || in fixVALUMaskWriteHazard()
2842 OpReg == AMDGPU::VCC_LO || in fixVALUMaskWriteHazard()
2843 OpReg == AMDGPU::VCC_HI) in fixVALUMaskWriteHazard()
2847 if (TRI.isSGPRReg(MRI, OpReg)) in fixVALUMaskWriteHazard()
H A DAMDGPURegisterBankInfo.cpp879 Register OpReg = Op.getReg(); in executeInWaterfallLoop() local
880 LLT OpTy = MRI.getType(OpReg); in executeInWaterfallLoop()
882 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop()
886 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
887 MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank); in executeInWaterfallLoop()
891 Register CurrentLaneReg = buildReadFirstLane(B, MRI, OpReg); in executeInWaterfallLoop()
903 OpParts.push_back(OpReg); in executeInWaterfallLoop()
906 auto UnmergeOp = B.buildUnmerge(PartTy, OpReg); in executeInWaterfallLoop()
3593 Register OpReg = MI.getOperand(I).getReg(); in getImageMapping() local
3595 if (!OpReg) in getImageMapping()
[all …]
H A DAMDGPUInstructionSelector.cpp2694 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2705 BuildMI(*BB, &MI, DL, TII.get(Opc), OpReg) in selectG_FNEG()
2712 .addReg(OpReg) in selectG_FNEG()
2732 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2747 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_AND_B32), OpReg) in selectG_FABS()
2754 .addReg(OpReg) in selectG_FABS()
H A DSIInstrInfo.cpp6107 Register OpReg = Op.getReg(); in legalizeGenericOperand() local
6111 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
6123 MachineInstr *Def = MRI.getVRegDef(OpReg); in legalizeGenericOperand()
6129 FoldImmediate(*Copy, *Def, OpReg, &MRI); in legalizeGenericOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1680 Register OpReg = getRegForValue(In); in selectFNeg() local
1681 if (!OpReg) in selectFNeg()
1687 OpReg); in selectFNeg()
1702 ISD::BITCAST, OpReg); in selectFNeg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4611 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSge() local
4628 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4748 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSle() local
4765 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
5439 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSeq() local
5443 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSeq()
5444 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5449 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSeq()
5520 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSne() local
5524 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSne()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp1999 Register OpReg = MO.getReg(); in clearRegisterKills() local
2000 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5691 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
5693 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract()
5757 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
5759 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert()
5763 if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarInsert()
5766 DstRegs.push_back(OpReg); in narrowScalarInsert()
5798 Register SegReg = OpReg; in narrowScalarInsert()
5802 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); in narrowScalarInsert()
8030 Register OpReg = MI.getOperand(1).getReg(); in lowerAbsToAddXor() local
8033 auto Shift = MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); in lowerAbsToAddXor()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
252 return getVectorRegSize(OpReg) / ScalarSize; in getRegOperandNumElts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7745 Register OpReg = MO.getReg(); in fixupPHIOpBanks() local
7746 const RegisterBank *RB = MRI.getRegBankOrNull(OpReg); in fixupPHIOpBanks()
7749 auto *OpDef = MRI.getVRegDef(OpReg); in fixupPHIOpBanks()
7750 const LLT &Ty = MRI.getType(OpReg); in fixupPHIOpBanks()
7759 auto Copy = MIB.buildCopy(Ty, OpReg); in fixupPHIOpBanks()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7362 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
7363 if (OpReg == Reg) in checkLowRegisterList()
7366 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
7376 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
7377 if (OpReg == Reg) in listContainsReg()