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Searched refs:OpDesc (Results 1 – 4 of 4) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h571 ComponentProps(const MCInstrDesc &OpDesc);
714 ComponentInfo(const MCInstrDesc &OpDesc,
716 : ComponentLayout(Kind), ComponentProps(OpDesc) {} in ComponentLayout()
719 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps) in ComponentInfo() argument
720 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {} in ComponentInfo()
1428 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1431 bool isDPALU_DPP(const MCInstrDesc &OpDesc);
H A DAMDGPUBaseInfo.cpp604 ComponentProps::ComponentProps(const MCInstrDesc &OpDesc) { in ComponentProps() argument
605 assert(OpDesc.getNumDefs() == Component::DST_NUM); in ComponentProps()
607 assert(OpDesc.getOperandConstraint(Component::SRC0, MCOI::TIED_TO) == -1); in ComponentProps()
608 assert(OpDesc.getOperandConstraint(Component::SRC1, MCOI::TIED_TO) == -1); in ComponentProps()
613 SrcOperandsNum = OpDesc.getNumOperands() - OpDesc.getNumDefs(); in ComponentProps()
616 auto OperandsNum = OpDesc.getNumOperands(); in ComponentProps()
2925 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc) { in hasAny64BitVGPROperands() argument
2928 int Idx = getNamedOperandIdx(OpDesc.getOpcode(), OpName); in hasAny64BitVGPROperands()
2932 if (OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64RegClassID || in hasAny64BitVGPROperands()
2940 bool isDPALU_DPP(const MCInstrDesc &OpDesc) { in isDPALU_DPP() argument
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/FuzzMutate/
H A DIRMutator.cpp142 auto OpDesc = chooseOperation(Srcs[0], IB); in mutate() local
144 if (!OpDesc) in mutate()
147 for (const auto &Pred : ArrayRef(OpDesc->SourcePreds).slice(1)) in mutate()
150 if (Value *Op = OpDesc->BuilderFunc(Srcs, Insts[IP])) { in mutate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1743 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); in storeRegToStackSlot() local
1751 BuildMI(MBB, MI, DL, OpDesc) in storeRegToStackSlot()
1970 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize)); in loadRegFromStackSlot() local
1978 BuildMI(MBB, MI, DL, OpDesc, DestReg) in loadRegFromStackSlot()
2291 const MCInstrDesc &OpDesc = get(Opc); in expandPostRAPseudo() local
2298 BuildMI(MBB, MI, DL, OpDesc) in expandPostRAPseudo()
2305 OpDesc.getNumOperands() + OpDesc.implicit_uses().size(); in expandPostRAPseudo()
2334 const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect_write); in expandPostRAPseudo() local
2336 BuildMI(MBB, MI, DL, OpDesc) in expandPostRAPseudo()
2344 OpDesc.getNumOperands() + OpDesc.implicit_uses().size(); in expandPostRAPseudo()