604 ComponentProps::ComponentProps(const MCInstrDesc &OpDesc) {  in ComponentProps()  argument
605   assert(OpDesc.getNumDefs() == Component::DST_NUM);  in ComponentProps()
607   assert(OpDesc.getOperandConstraint(Component::SRC0, MCOI::TIED_TO) == -1);  in ComponentProps()
608   assert(OpDesc.getOperandConstraint(Component::SRC1, MCOI::TIED_TO) == -1);  in ComponentProps()
609   auto TiedIdx = OpDesc.getOperandConstraint(Component::SRC2, MCOI::TIED_TO);  in ComponentProps()
613   SrcOperandsNum = OpDesc.getNumOperands() - OpDesc.getNumDefs();  in ComponentProps()
616   auto OperandsNum = OpDesc.getNumOperands();  in ComponentProps()
619     if (OpDesc.operands()[CompOprIdx].OperandType == AMDGPU::OPERAND_KIMM32) {  in ComponentProps()
2925 bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc) {  in hasAny64BitVGPROperands()  argument
2928     int Idx = getNamedOperandIdx(OpDesc.getOpcode(), OpName);  in hasAny64BitVGPROperands()
2932     if (OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64RegClassID ||  in hasAny64BitVGPROperands()
2933         OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)  in hasAny64BitVGPROperands()
2940 bool isDPALU_DPP(const MCInstrDesc &OpDesc) {  in isDPALU_DPP()  argument
2941   return hasAny64BitVGPROperands(OpDesc);  in isDPALU_DPP()