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Searched refs:NumVecs (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1577 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1613 if (NumVecs == 1) in SelectPostLoad()
1751 for (unsigned i = 0; i < NumVecs; ++i) in SelectCVTIntrinsic()
1790 for (unsigned i = 0; i < NumVecs; ++i) in SelectDestructiveMultiIntrinsic()
1820 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1825 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1855 for (unsigned i = 0; i < NumVecs; ++i) in SelectContiguousMultiVectorLoad()
1860 unsigned ChainIdx = NumVecs; in SelectContiguousMultiVectorLoad()
1914 for (unsigned i = 0; i < NumVecs; ++i) in SelectClamp()
1978 unsigned ChainIdx = NumVecs; in SelectMultiVectorMove()
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H A DAArch64ISelLowering.cpp14458 template <unsigned NumVecs>
14468 for (unsigned I = 0; I < NumVecs; ++I) in setInfoSVEStN()
21784 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
21789 NumVecs = 2; break; in performNEONPostLDSTCombine()
21791 NumVecs = 3; break; in performNEONPostLDSTCombine()
21793 NumVecs = 4; break; in performNEONPostLDSTCombine()
21795 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
21797 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
21801 NumVecs = 2; break; in performNEONPostLDSTCombine()
21803 NumVecs = 3; break; in performNEONPostLDSTCombine()
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H A DAArch64TargetTransformInfo.cpp3755 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; in getShuffleCost() local
3759 for (unsigned N = 0; N < NumVecs; N++) { in getShuffleCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2114 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2152 if (NumVecs == 1) in SelectVLD()
2155 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2231 if (NumVecs == 1) { in SelectVLD()
2256 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2429 if (NumVecs != 3) { in SelectVLDSTLane()
2463 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2489 if (NumVecs == 2) { in SelectVLDSTLane()
2953 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2966 if (NumVecs != 3) { in SelectVLDDup()
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H A DARMISelLowering.cpp15798 NumVecs = 1; in TryCombineBaseUpdate()
15802 NumVecs = 2; in TryCombineBaseUpdate()
15806 NumVecs = 3; in TryCombineBaseUpdate()
15810 NumVecs = 4; in TryCombineBaseUpdate()
15814 NumVecs = 2; in TryCombineBaseUpdate()
15819 NumVecs = 3; in TryCombineBaseUpdate()
15824 NumVecs = 4; in TryCombineBaseUpdate()
15829 NumVecs = 2; in TryCombineBaseUpdate()
16379 NumVecs = 2; in CombineVLDDUP()
16382 NumVecs = 3; in CombineVLDDUP()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp862 unsigned NumVecs) { in createInterleaveMask() argument
865 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
937 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
938 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
944 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
946 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
953 if (NumVecs % 2 != 0) in concatenateVectors()
954 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
957 NumVecs = ResList.size(); in concatenateVectors()
958 } while (NumVecs > 1); in concatenateVectors()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp6008 assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors"); in selectVectorLoadIntrinsic()
6021 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in selectVectorLoadIntrinsic()
6033 unsigned Opc, unsigned NumVecs, MachineInstr &I) { in selectVectorLoadLaneIntrinsic() argument
6036 assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors"); in selectVectorLoadLaneIntrinsic()
6041 auto FirstSrcRegIt = I.operands_begin() + NumVecs + 1; in selectVectorLoadLaneIntrinsic()
6042 SmallVector<Register, 4> Regs(NumVecs); in selectVectorLoadLaneIntrinsic()
6069 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in selectVectorLoadLaneIntrinsic()
6090 Register Ptr = I.getOperand(1 + NumVecs).getReg(); in selectVectorStoreIntrinsic()
6092 SmallVector<Register, 2> Regs(NumVecs); in selectVectorStoreIntrinsic()
6104 MachineInstr &I, unsigned NumVecs, unsigned Opc) { in selectVectorStoreLaneIntrinsic() argument
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h353 llvm::SmallVector<int, 16> createInterleaveMask(unsigned VF, unsigned NumVecs);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp10781 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
10784 NumVecs = 4; in LowerINTRINSIC_WO_CHAIN()
10788 for (int VecNo = 0; VecNo < NumVecs; VecNo++) { in LowerINTRINSIC_WO_CHAIN()
10791 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
11364 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
11365 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorLoad()
11410 unsigned NumVecs = 2; in LowerVectorStore() local
11421 NumVecs = 4; in LowerVectorStore()
11423 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorStore()
11424 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
/freebsd-14.2/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp17434 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
17437 NumVecs = 4; in EmitPPCBuiltinExpr()
17446 for (unsigned i=0; i<NumVecs; i++) { in EmitPPCBuiltinExpr()