217   void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
225   void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
233                        unsigned NumVecs, const uint16_t *DOpcodes,
290   void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
311                     unsigned NumVecs, const uint16_t *DOpcodes,
350   SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1939                                        unsigned NumVecs, bool is64BitVector) {  in GetVLDSTAlign()  argument
1940   unsigned NumRegs = NumVecs;  in GetVLDSTAlign()
1941   if (!is64BitVector && NumVecs < 3)  in GetVLDSTAlign()
2104 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {  in isPerfectIncrement()  argument
2106   return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;  in isPerfectIncrement()
2109 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,  in SelectVLD()  argument
2114   assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");  in SelectVLD()
2127   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVLD()
2152   if (NumVecs == 1)  in SelectVLD()
2155     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLD()
2172   if (is64BitVector || NumVecs <= 2) {  in SelectVLD()
2179       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);  in SelectVLD()
2231   if (NumVecs == 1) {  in SelectVLD()
2242   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)  in SelectVLD()
2245   ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));  in SelectVLD()
2247     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));  in SelectVLD()
2251 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,  in SelectVST()  argument
2256   assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");  in SelectVST()
2272   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVST()
2306   if (is64BitVector || NumVecs <= 2) {  in SelectVST()
2308     if (NumVecs == 1) {  in SelectVST()
2314       if (NumVecs == 2)  in SelectVST()
2320         SDValue V3 = (NumVecs == 3)  in SelectVST()
2338       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);  in SelectVST()
2371   SDValue V3 = (NumVecs == 3)  in SelectVST()
2406                                       unsigned NumVecs,  in SelectVLDSTLane()  argument
2410   assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");  in SelectVLDSTLane()
2424   unsigned Lane = N->getConstantOperandVal(Vec0Idx + NumVecs);  in SelectVLDSTLane()
2429   if (NumVecs != 3) {  in SelectVLDSTLane()
2431     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;  in SelectVLDSTLane()
2463     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLDSTLane()
2482         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);  in SelectVLDSTLane()
2489   if (NumVecs == 2) {  in SelectVLDSTLane()
2496     SDValue V3 = (NumVecs == 3)  in SelectVLDSTLane()
2525   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)  in SelectVLDSTLane()
2528   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));  in SelectVLDSTLane()
2530     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));  in SelectVLDSTLane()
2785 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,  in SelectMVE_VLD()  argument
2806   EVT DataTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs * 2);  in SelectMVE_VLD()
2814   for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) {  in SelectMVE_VLD()
2827       CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);  in SelectMVE_VLD()
2831   for (i = 0; i < NumVecs; i++)  in SelectMVE_VLD()
2948                                    bool isUpdating, unsigned NumVecs,  in SelectVLDDup()  argument
2953   assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");  in SelectVLDDup()
2966   if (NumVecs != 3) {  in SelectVLDDup()
2968     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;  in SelectVLDDup()
3000   unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLDDup()
3018                  : (NumVecs == 1) ? QOpcodes0[OpcodeIndex]  in SelectVLDDup()
3023         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);  in SelectVLDDup()
3033   if (is64BitVector || NumVecs == 1) {  in SelectVLDDup()
3035   } else if (NumVecs == 2) {  in SelectVLDDup()
3061   if (NumVecs == 1) {  in SelectVLDDup()
3067     for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {  in SelectVLDDup()
3072   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));  in SelectVLDDup()
3074     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));  in SelectVLDDup()