Searched refs:MFMA (Results 1 – 7 of 7) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNHazardRecognizer.cpp | 2444 MFMA = &MI; in checkMAIVALUHazards()
2532 MFMA = nullptr; in checkMAIVALUHazards()
2535 if (!MFMA) in checkMAIVALUHazards()
2544 ? isXDL(ST, *MFMA) in checkMAIVALUHazards()
2634 MFMA = nullptr; in checkMAIVALUHazards()
2637 if (MFMA) { in checkMAIVALUHazards()
2642 ? isXDL(ST, *MFMA) in checkMAIVALUHazards()
2657 ? isXDL(ST, *MFMA) in checkMAIVALUHazards()
2695 MFMA = &MI; in checkMAIVALUHazards()
2699 MFMA = nullptr; in checkMAIVALUHazards()
[all …]
|
| H A D | AMDGPUIGroupLP.cpp | 71 MFMA = 1u << 3, enumerator
902 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1232 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1242 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1268 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1279 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1297 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1318 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1332 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1343 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
[all …]
|
| H A D | SISchedule.td | 126 def HWXDL : ProcResource<1> { // MFMA CU
|
| H A D | SIInstrFormats.td | 136 // This bit indicates that this is one of MFMA instructions.
|
| H A D | AMDGPU.td | 191 "MFMA cannot use inline literal as SrcC"
|
| /freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | BuiltinsAMDGPU.def | 345 // MFMA builtins.
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 281 // MASK = 0x0000 0008: MFMA/WMMA instructions may be scheduled across SCHED_BARRIER.
3052 // Note: in gfx940 BLGP argument is replaced by NEG bitfield in the DGEMM MFMA.
|