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Searched refs:LMul (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td153 vti.LMul, vti.AVL, vti.RegClass,
166 vti.LMul, vti.AVL, vti.RegClass,
554 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
570 (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
860 defvar suffix = vti.LMul.MX;
966 (!cast<Instruction>("PseudoVWADD_VV_"#vti.LMul.MX)
1011 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
1161 (!cast<Instruction>("PseudoVMAND_MM_"#mti.LMul.MX)
1164 (!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX)
1167 (!cast<Instruction>("PseudoVMXOR_MM_"#mti.LMul.MX)
[all …]
H A DRISCVInstrInfoZvk.td439 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX)
447 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
488 (!cast<Instruction>("PseudoVROR_VI_"#vti.LMul.MX)
505 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX)
512 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX)
519 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX)
722 vti.LMul, vti.RegClass, vti.RegClass>;
731 vti.LMul, vti_vs2.LMul, vti.RegClass, vti_vs2.RegClass>;
782 instruction#"_"#kind#"_"#vti.LMul.MX),
795 instruction#"_VI_"#vti.LMul.MX));
[all …]
H A DRISCVInstrInfoVVLPatterns.td1637 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
1670 defvar suffix = vti.LMul.MX;
1700 defvar suffix = vti.LMul.MX;
1791 defvar suffix = vti.LMul.MX;
1813 defvar suffix = vti.LMul.MX;
1843 defvar suffix = vti.LMul.MX;
1879 defvar suffix = vti.LMul.MX;
2351 (!cast<Instruction>(inst#"_WI_"#vti.LMul.MX#"_MASK")
2584 fvti.LMul.MX)
2836 defvar vlmul = vti.LMul;
[all …]
H A DRISCVInstrInfoVPseudos.td267 LMULInfo LMul = M;
395 LMULInfo LMul = M;
1898 defvar mx = mti.LMul.MX;
1900 let VLMul = mti.LMul.value in {
1973 defvar mx = mti.LMul.MX;
1975 let VLMul = mti.LMul.value in {
2027 defvar mx = mti.LMul.MX;
2028 let VLMul = mti.LMul.value in {
2039 defvar mx = mti.LMul.MX;
2052 defvar mx = mti.LMul.MX;
[all …]
H A DRISCVInstrInfoXSf.td501 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
505 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
509 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
518 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
522 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
526 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
535 "PseudoVC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
539 "PseudoVC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
543 "PseudoVC_V_" # instruction_suffix # "_" # vti.LMul.MX,
570 Vs2Info.Log2SEW, Vs2Info.LMul,
[all …]
H A DRISCVInsertVSETVLI.cpp813 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMul); in computeVLMAX()
815 VLEN = VLEN / LMul; in computeVLMAX()
817 VLEN = VLEN * LMul; in computeVLMAX()
1000 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL); in isLMUL1OrSmaller()
1001 return Fractional || LMul == 1; in isLMUL1OrSmaller()
H A DRISCVInstrInfo.cpp170 RISCVII::VLMUL LMul) { in isConvertibleToVMV_V_V() argument
204 if (FirstLMul != LMul) in isConvertibleToVMV_V_V()
236 return LMul == RISCVVType::getVLMUL(VType); in isConvertibleToVMV_V_V()
305 RISCVII::VLMUL LMul; in copyPhysRegVector() local
312 LMul = RISCVII::LMUL_1; in copyPhysRegVector()
318 LMul = RISCVII::LMUL_2; in copyPhysRegVector()
324 LMul = RISCVII::LMUL_4; in copyPhysRegVector()
331 LMul = RISCVII::LMUL_8; in copyPhysRegVector()
341 if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { in copyPhysRegVector()
375 std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul); in copyPhysRegVector()
H A DRISCVISelLowering.h755 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
H A DRISCVInstrInfoXTHead.td511 vti.Mask, wti.Log2SEW, vti.LMul,
524 vti.Mask, wti.Log2SEW, vti.LMul,
H A DRISCVISelLowering.cpp2308 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) { in getRegClassIDForLMUL() argument
2309 switch (LMul) { in getRegClassIDForLMUL()
2493 unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen); in useRVVForFixedLengthVectorVT() local
2495 if (LMul > Subtarget.getMaxLMULForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
2688 unsigned LMul; in getLMULCost() local
2690 std::tie(LMul, Fractional) = in getLMULCost()
2693 Cost = LMul <= DLenFactor ? (DLenFactor / LMul) : 1; in getLMULCost()
2695 Cost = (LMul * DLenFactor); in getLMULCost()
8440 SDValue LMul = DAG.getTargetConstant(VLMUL, DL, XLenVT); in lowerGetVectorLength() local
16393 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMUL); in computeKnownBitsForTargetNode()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp180 unsigned LMul; in printVType() local
182 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType)); in printVType()
188 OS << LMul; in printVType()
202 unsigned LMul; in getSEWLMULRatio() local
204 std::tie(LMul, Fractional) = decodeVLMUL(VLMul); in getSEWLMULRatio()
207 LMul = Fractional ? (8 / LMul) : (LMul * 8); in getSEWLMULRatio()
210 return (SEW * 8) / LMul; in getSEWLMULRatio()