Lines Matching refs:LMul
2308 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) { in getRegClassIDForLMUL() argument
2309 switch (LMul) { in getRegClassIDForLMUL()
2493 unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen); in useRVVForFixedLengthVectorVT() local
2495 if (LMul > Subtarget.getMaxLMULForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
2688 unsigned LMul; in getLMULCost() local
2690 std::tie(LMul, Fractional) = in getLMULCost()
2693 Cost = LMul <= DLenFactor ? (DLenFactor / LMul) : 1; in getLMULCost()
2695 Cost = (LMul * DLenFactor); in getLMULCost()
8440 SDValue LMul = DAG.getTargetConstant(VLMUL, DL, XLenVT); in lowerGetVectorLength() local
8447 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, ID, AVL, Sew, LMul); in lowerGetVectorLength()
16393 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMUL); in computeKnownBitsForTargetNode()
16395 MaxVL = (Fractional) ? MaxVL / LMul : MaxVL * LMul; in computeKnownBitsForTargetNode()