| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetCallingConv.h | 29 unsigned IsZExt : 1; ///< Zero extended
63 : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsByRef(0), in ArgFlagsTy()
73 bool isZExt() const { return IsZExt; } in isZExt()
74 void setZExt() { IsZExt = 1; } in setZExt()
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| H A D | MachineFrameInfo.h | 540 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
543 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| H A D | TargetLowering.h | 301 bool IsZExt : 1; variable
318 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), in ArgListEntry()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 311 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
4008 if (IsZExt) { in emiti1Ext()
4257 if (!IsZExt) { in emitLSR_ri()
4263 IsZExt = true; in emitLSR_ri()
4524 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI))) in optimizeIntExtLoad()
4533 if (IsZExt) { in optimizeIntExtLoad()
4575 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { in selectIntExt()
4659 bool IsZExt = true; in selectMul() local
4665 IsZExt = true; in selectMul()
4729 IsZExt = true; in selectShift()
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| H A D | AArch64ISelLowering.cpp | 4373 Entry.IsZExt = false; in LowerFSINCOS()
16542 bool IsZExt = false; in performVecReduceAddCombineWithUADDLP() local
16544 IsZExt = true; in performVecReduceAddCombineWithUADDLP()
16546 IsZExt = false; in performVecReduceAddCombineWithUADDLP()
16567 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
16578 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 843 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() : in PPCEmitCmp()
845 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
918 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
920 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
924 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; in PPCEmitCmp()
926 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; in PPCEmitCmp()
1815 if (!IsZExt) { in PPCEmitIntExt()
1905 bool IsZExt = isa<ZExtInst>(I); in SelectIntExt() local
2308 bool IsZExt = false; in tryToFoldLoadIntoMI() local
2315 IsZExt = true; in tryToFoldLoadIntoMI()
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| H A D | PPCInstrInfo.cpp | 5197 bool IsZExt = definedByZeroExtendingOp(Reg, MRI); in isSignOrZeroExtended() local
5201 if (IsSExt && IsZExt) in isSignOrZeroExtended()
5202 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5227 IsZExt |= FuncInfo->isLiveInZExt(VReg); in isSignOrZeroExtended()
5228 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5264 IsZExt |= Attrs.hasAttribute(Attribute::ZExt); in isSignOrZeroExtended()
5265 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5319 IsZExt = true; in isSignOrZeroExtended()
5327 IsZExt &= SrcExt.second; in isSignOrZeroExtended()
5329 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
[all …]
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| H A D | PPCISelLowering.cpp | 18293 Entry.IsZExt = !Entry.IsSExt; in lowerToLibCall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 186 bool IsZExt);
1751 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1752 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1889 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1897 if (IsZExt) in emitIntExt()
1976 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
1977 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 783 bool IsZExt = (Ld->getExtensionType() == ISD::ZEXTLOAD); in tryIndexedLoad() local
786 Opcode = IsZExt ? RISCV::TH_LBUIB : RISCV::TH_LBIB; in tryIndexedLoad()
788 Opcode = IsZExt ? RISCV::TH_LBUIA : RISCV::TH_LBIA; in tryIndexedLoad()
790 Opcode = IsZExt ? RISCV::TH_LHUIB : RISCV::TH_LHIB; in tryIndexedLoad()
792 Opcode = IsZExt ? RISCV::TH_LHUIA : RISCV::TH_LHIA; in tryIndexedLoad()
794 Opcode = IsZExt ? RISCV::TH_LWUIB : RISCV::TH_LWIB; in tryIndexedLoad()
796 Opcode = IsZExt ? RISCV::TH_LWUIA : RISCV::TH_LWIA; in tryIndexedLoad()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 1026 bool IsZExt = isa<ZExtInst>(CastOp); in foldBinOpOfSelectAndCastOfSelectCondition() local
1031 } else if (IsZExt) { in foldBinOpOfSelectAndCastOfSelectCondition()
3340 bool IsZExt = isa<ZExtInst>(Cond); in visitSwitchInst() local
3346 return IsZExt ? CaseVal.isIntN(NewWidth) in visitSwitchInst()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2105 Entry.IsZExt = !Entry.IsSExt; in ExpandLibCall()
2257 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2266 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2349 Entry.IsZExt = false; in ExpandSinCosLibCall()
2357 Entry.IsZExt = false; in ExpandSinCosLibCall()
2365 Entry.IsZExt = false; in ExpandSinCosLibCall()
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| H A D | FastISel.cpp | 1029 if (Arg.IsZExt) in lowerCallTo()
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| H A D | SelectionDAGBuilder.cpp | 10331 Entry.IsZExt = false; in LowerCallTo()
10433 if (Args[i].IsZExt) in LowerCallTo()
10512 else if (Args[i].IsZExt) in LowerCallTo()
10536 CLI.RetZExt == Args[i].IsZExt)) in LowerCallTo()
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| H A D | LegalizeIntegerTypes.cpp | 4850 Entry.IsZExt = false; in ExpandIntRes_XMULO()
4858 Entry.IsZExt = false; in ExpandIntRes_XMULO()
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| H A D | TargetLowering.cpp | 114 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); in setAttributes()
163 Entry.IsZExt = !Entry.IsSExt; in makeLibCall()
167 Entry.IsSExt = Entry.IsZExt = false; in makeLibCall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 586 Entry.IsZExt = !IsSigned; in LowerDivRem()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9943 Entry.IsZExt = false; in LowerFSINCOS()
9953 Entry.IsZExt = false; in LowerFSINCOS()
20687 Entry.IsZExt = !isSigned; in getDivRemArgList()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2107 Entry.IsZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), IsSigned); in makeExternalCall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 21290 Entry.IsZExt = true; in LowerFP_EXTEND()
21400 Entry.IsZExt = true; in LowerFP_ROUND()
28745 Entry.IsZExt = false; in LowerWin64_i128OP()
31420 Entry.IsZExt = false; in LowerFSINCOS()
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