Lines Matching refs:IsZExt
205 bool WantResult = true, bool IsZExt = false);
223 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
224 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
237 bool IsZExt = false);
241 bool IsZExt = false);
259 bool IsZExt = true);
262 bool IsZExt = true);
265 bool IsZExt = false);
304 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
311 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
1166 bool WantResult, bool IsZExt) { in emitAddSub() argument
1177 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; in emitAddSub()
1181 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
1213 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1217 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue(); in emitAddSub()
1293 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1466 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) { in emitCmp() argument
1481 return emitICmp(VT, LHS, RHS, IsZExt); in emitCmp()
1489 bool IsZExt) { in emitICmp() argument
1491 IsZExt) != 0; in emitICmp()
1533 bool SetFlags, bool WantResult, bool IsZExt) { in emitAdd() argument
1535 IsZExt); in emitAdd()
1562 bool SetFlags, bool WantResult, bool IsZExt) { in emitSub() argument
1564 IsZExt); in emitSub()
3909 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
3910 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
4000 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) { in emiti1Ext() argument
4008 if (IsZExt) { in emiti1Ext()
4092 uint64_t Shift, bool IsZExt) { in emitLSL_ri() argument
4117 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4156 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSL_ri()
4195 uint64_t Shift, bool IsZExt) { in emitLSR_ri() argument
4220 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4252 if (Shift >= SrcBits && IsZExt) in emitLSR_ri()
4257 if (!IsZExt) { in emitLSR_ri()
4258 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4263 IsZExt = true; in emitLSR_ri()
4272 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSR_ri()
4311 uint64_t Shift, bool IsZExt) { in emitASR_ri() argument
4336 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4368 if (Shift >= SrcBits && IsZExt) in emitASR_ri()
4377 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitASR_ri()
4391 bool IsZExt) { in emitIntExt() argument
4411 return emiti1Ext(SrcReg, DestVT, IsZExt); in emitIntExt()
4414 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4416 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4421 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4423 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4428 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4516 bool IsZExt = isa<ZExtInst>(I); in optimizeIntExtLoad() local
4524 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI))) in optimizeIntExtLoad()
4533 if (IsZExt) { in optimizeIntExtLoad()
4573 bool IsZExt = isa<ZExtInst>(I); in selectIntExt() local
4575 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { in selectIntExt()
4591 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4659 bool IsZExt = true; in selectMul() local
4665 IsZExt = true; in selectMul()
4674 IsZExt = false; in selectMul()
4685 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4722 bool IsZExt = I->getOpcode() != Instruction::AShr; in selectShift() local
4729 IsZExt = true; in selectShift()
4738 IsZExt = false; in selectShift()
4751 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
4754 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
4757 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()