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Searched refs:IsRV64 (Results 1 – 25 of 29) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp53 bool parseCPU(StringRef CPU, bool IsRV64) { in parseCPU() argument
58 return Info->is64Bit() == IsRV64; in parseCPU()
61 bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) { in parseTuneCPU() argument
72 return parseCPU(TuneCPU, IsRV64); in parseTuneCPU()
82 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidCPUArchList() argument
84 if (IsRV64 == C.is64Bit()) in fillValidCPUArchList()
89 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) { in fillValidTuneCPUArchList() argument
91 if (IsRV64 == C.is64Bit()) in fillValidTuneCPUArchList()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZk.td87 let Predicates = [HasStdExtZknd, IsRV64] in {
92 } // Predicates = [HasStdExtZknd, IsRV64]
105 let Predicates = [HasStdExtZkne, IsRV64] in {
108 } // Predicates = [HasStdExtZkne, IsRV64]
126 let Predicates = [HasStdExtZknh, IsRV64] in {
131 } // Predicates = [HasStdExtZknh, IsRV64]
157 let Predicates = [HasStdExtZknd, IsRV64] in {
161 } // Predicates = [HasStdExtZknd, IsRV64]
175 let Predicates = [HasStdExtZkne, IsRV64] in {
178 } // Predicates = [HasStdExtZkne, IsRV64]
[all …]
H A DRISCVInstrInfoM.td49 let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in {
52 } // Predicates = [HasStdExtMOrZmmul, IsRV64]
54 let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in {
63 } // Predicates = [HasStdExtM, IsRV64]
84 let Predicates = [HasStdExtMOrZmmul, IsRV64] in
87 let Predicates = [HasStdExtM, IsRV64] in {
107 } // Predicates = [HasStdExtM, IsRV64]
109 let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in {
116 } // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba]
122 let Predicates = [HasStdExtMOrZmmul, IsRV64] in {
[all …]
H A DRISCVInstrInfoA.td74 let Predicates = [HasStdExtA, IsRV64] in {
96 } // Predicates = [HasStdExtA, IsRV64]
115 let Predicates = [HasAtomicLdSt, IsRV64] in {
160 defm : AMOPat<"atomic_swap_64", "AMOSWAP_D", i64, [IsRV64]>;
163 defm : AMOPat<"atomic_load_or_64", "AMOOR_D", i64, [IsRV64]>;
272 let Predicates = [HasStdExtA, IsRV64] in {
305 } // Predicates = [HasStdExtA, IsRV64]
341 let Predicates = [HasStdExtA, NoStdExtZacas, IsRV64] in {
364 let Predicates = [HasStdExtA, IsRV64] in {
369 } // Predicates = [HasStdExtA, IsRV64]
[all …]
H A DRISCVInstrInfoZb.td334 } // Predicates = [HasStdExtZba, IsRV64]
404 } // Predicates = [HasStdExtZbb, IsRV64]
456 } // Predicates = [HasStdExtZbb, IsRV64]
491 } // Predicates = [HasStdExtZba, IsRV64]
501 } // Predicates = [HasStdExtZbb, IsRV64]
618 } // Predicates = [HasStdExtZbb, IsRV64]
668 } // Predicates = [HasStdExtZbkb, IsRV64]
807 } // Predicates = [HasStdExtZba, IsRV64]
840 } // Predicates = [HasStdExtZbb, IsRV64]
868 } // Predicates = [HasStdExtZbkb, IsRV64]
[all …]
H A DRISCVInstrInfoXVentana.td17 let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
31 let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
45 } // Predicates = [IsRV64, HasVendorXVentanaCondOps]
H A DRISCVInstrInfoD.td207 let Predicates = [HasStdExtZdinx, IsRV64] in {
219 } // Predicates = [HasStdExtZdinx, IsRV64]
248 let Predicates = [HasStdExtZdinx, IsRV64] in {
254 } // Predicates = [HasStdExtZdinx, IsRV64]
312 let Predicates = [HasStdExtZdinx, IsRV64] in {
347 } // Predicates = [HasStdExtZdinx, IsRV64]
448 } // Predicates = [HasStdExtZdinx, IsRV64]
509 } // Predicates = [HasStdExtZdinx, IsRV64]
585 let Predicates = [HasStdExtD, IsRV64] in {
620 } // Predicates = [HasStdExtD, IsRV64]
[all …]
H A DRISCVInstrInfoZfh.td173 "fcvt.l.h", [IsRV64]>,
177 "fcvt.lu.h", [IsRV64]>,
181 "fcvt.h.l", [IsRV64]>,
185 "fcvt.h.lu", [IsRV64]>,
504 let Predicates = [HasStdExtZfh, IsRV64] in {
532 } // Predicates = [HasStdExtZfh, IsRV64]
534 let Predicates = [HasStdExtZhinx, IsRV64] in {
562 } // Predicates = [HasStdExtZhinx, IsRV64]
632 let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
648 } // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]
[all …]
H A DRISCVInstrInfoXTHead.td269 } // Predicates = [HasVendorXTHeadBb, IsRV64]
294 } // Predicates = [HasVendorXTHeadMac, IsRV64]
306 let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {
627 let Predicates = [HasVendorXTHeadBb, IsRV64] in {
637 } // Predicates = [HasVendorXTHeadBb, IsRV64]
675 let Predicates = [HasVendorXTHeadMac, IsRV64] in {
690 } // Predicates = [HasVendorXTHeadMac, IsRV64]
735 let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {
829 let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {
894 let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {
[all …]
H A DRISCVInstrInfoC.td344 let Predicates = [HasStdExtCOrZca, IsRV64] in
378 let Predicates = [HasStdExtCOrZca, IsRV64] in
418 Predicates = [HasStdExtCOrZca, IsRV64] in
528 let Predicates = [HasStdExtCOrZca, IsRV64] in
586 let Predicates = [HasStdExtCOrZca, IsRV64] in
870 } // Predicates = [HasStdExtCOrZca, IsRV64]
890 } // Predicates = [HasStdExtCOrZca, IsRV64]
907 } // Predicates = [HasStdExtCOrZca, IsRV64]
952 } // Predicates = [HasStdExtCOrZca, IsRV64]
993 } // Predicates = [HasStdExtCOrZca, IsRV64]
[all …]
H A DRISCVInstrInfoZa.td65 let Predicates = [HasStdExtZacas, IsRV64] in {
68 } // Predicates = [HasStdExtZacas, IsRV64]
119 defm : AMOCASPat<"atomic_cmp_swap_64", "AMOCAS_D_RV64", i64, [IsRV64]>;
H A DRISCVInstrInfoZc.td144 let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in
254 let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{
257 } // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64]
H A DRISCVInstrInfoF.td369 "fcvt.l.s", [IsRV64]>,
373 "fcvt.lu.s", [IsRV64]>,
377 "fcvt.s.l", [IsRV64]>,
381 "fcvt.s.lu", [IsRV64]>,
513 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
735 let Predicates = [HasStdExtF, IsRV64] in {
767 } // Predicates = [HasStdExtF, IsRV64]
769 let Predicates = [HasStdExtZfinx, IsRV64] in {
801 } // Predicates = [HasStdExtZfinx, IsRV64]
H A DRISCVInstrInfo.td744 let Predicates = [IsRV64] in {
771 } // Predicates = [IsRV64]
874 let Predicates = [IsRV64] in {
878 } // Predicates = [IsRV64]
885 let Predicates = [IsRV64] in {
888 } // Predicates = [IsRV64]
1026 let Predicates = [IsRV64] in {
1042 } // Predicates = [IsRV64]
1948 let Predicates = [IsRV64] in {
2008 } // Predicates = [IsRV64]
[all …]
H A DRISCVGISel.td89 let Predicates = [IsRV64] in {
156 let Predicates = [IsRV64] in {
H A DRISCVInstrInfoZicfiss.td62 let Predicates = [HasStdExtZicfiss, IsRV64] in
H A DRISCVSubtarget.h163 bool is64Bit() const { return IsRV64; } in is64Bit()
H A DRISCVInstrInfoZfbfmin.td76 let Predicates = [HasStdExtZfbfmin, IsRV64] in {
H A DRISCVFrameLowering.cpp72 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSPrologue() local
82 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue()
127 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSEpilogue() local
132 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h28 bool parseCPU(StringRef CPU, bool IsRV64);
29 bool parseTuneCPU(StringRef CPU, bool IsRV64);
31 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
32 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp42 bool IsRV64 = TT.isArch64Bit(); in computeTargetABI() local
49 } else if (ABIName.starts_with("ilp32") && IsRV64) { in computeTargetABI()
53 } else if (ABIName.starts_with("lp64") && !IsRV64) { in computeTargetABI()
57 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E && in computeTargetABI()
63 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E && in computeTargetABI()
72 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) && in computeTargetABI()
80 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
123 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
124 unsigned XLen = IsRV64 ? 64 : 32; in parseFeatureBits()
H A DRISCVBaseInfo.h483 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
599 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64, in getStackAdjBase() argument
605 if (!IsRV64) { in getStackAdjBase()
651 int64_t StackAdjustment, bool IsRV64, bool IsEABI) { in getSpimm() argument
654 unsigned stackAdj = getStackAdjBase(RlistVal, IsRV64, IsEABI); in getSpimm()
H A DRISCVMatInt.cpp50 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in generateInstSeqImpl() local
74 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
80 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); in generateInstSeqImpl()
474 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in getIntMatCost() local
477 int PlatRegSize = IsRV64 ? 64 : 32; in getIntMatCost()
H A DRISCVInstPrinter.cpp299 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in printSpimm() local
304 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64, IsEABI); in printSpimm()
/freebsd-14.2/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DRISCVToolchain.cpp159 bool IsRV64 = ToolChain.getArch() == llvm::Triple::riscv64; in ConstructJob() local
161 if (IsRV64) { in ConstructJob()

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