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Searched refs:IsFSHL (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2105 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits() local
2130 Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt)); in SimplifyDemandedBits()
2131 Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt)); in SimplifyDemandedBits()
2132 Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); in SimplifyDemandedBits()
2133 Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); in SimplifyDemandedBits()
7787 bool IsFSHL = Node->getOpcode() == ISD::VP_FSHL; in expandVPFunnelShift() local
7820 if (IsFSHL) { in expandVPFunnelShift()
7851 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift() local
7857 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
7869 if (IsFSHL) { in expandFunnelShift()
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H A DDAGCombiner.cpp10768 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift() local
10776 return IsFSHL ? N0 : N1; in visitFunnelShift()
10795 return IsFSHL ? N0 : N1; in visitFunnelShift()
10803 DAG.getConstant(IsFSHL ? BitWidth - ShAmt : ShAmt, in visitFunnelShift()
10807 DAG.getConstant(IsFSHL ? ShAmt : BitWidth - ShAmt, in visitFunnelShift()
10826 IsFSHL ? (((BitWidth - ShAmt) % BitWidth) / 8) : (ShAmt / 8); in visitFunnelShift()
10856 if (IsUndefOrZero(N0) && !IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits)) in visitFunnelShift()
10858 if (IsUndefOrZero(N1) && IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits)) in visitFunnelShift()
10866 unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR; in visitFunnelShift()
H A DSelectionDAGBuilder.cpp6818 bool IsFSHL = Intrinsic == Intrinsic::fshl; in visitIntrinsicCall() local
6825 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR; in visitIntrinsicCall()
6828 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6228 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; in lowerFunnelShiftWithInverse() local
6229 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; in lowerFunnelShiftWithInverse()
6240 if (IsFSHL) { in lowerFunnelShiftWithInverse()
6263 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; in lowerFunnelShiftAsShifts() local
6276 ShX = MIRBuilder.buildShl(Ty, X, IsFSHL ? ShAmt : InvShAmt).getReg(0); in lowerFunnelShiftAsShifts()
6277 ShY = MIRBuilder.buildLShr(Ty, Y, IsFSHL ? InvShAmt : ShAmt).getReg(0); in lowerFunnelShiftAsShifts()
6295 if (IsFSHL) { in lowerFunnelShiftAsShifts()
6321 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; in lowerFunnelShift() local
6322 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; in lowerFunnelShift()
H A DCombinerHelper.cpp4168 bool IsFSHL = Opc == TargetOpcode::G_FSHL; in applyFunnelShiftToRotate() local
4170 MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL in applyFunnelShiftToRotate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp9067 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift() local
9081 X = DAG.getNode(PPCISD::SHL, dl, VT, X, IsFSHL ? Z : SubZ); in LowerFunnelShift()
9082 Y = DAG.getNode(PPCISD::SRL, dl, VT, Y, IsFSHL ? SubZ : Z); in LowerFunnelShift()