Lines Matching refs:IsFSHL
2105 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits() local
2113 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts, in SimplifyDemandedBits()
2121 APInt Demanded0 = DemandedBits.lshr(IsFSHL ? Amt : (BitWidth - Amt)); in SimplifyDemandedBits()
2122 APInt Demanded1 = DemandedBits << (IsFSHL ? (BitWidth - Amt) : Amt); in SimplifyDemandedBits()
2130 Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt)); in SimplifyDemandedBits()
2131 Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt)); in SimplifyDemandedBits()
2132 Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); in SimplifyDemandedBits()
2133 Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt); in SimplifyDemandedBits()
7787 bool IsFSHL = Node->getOpcode() == ISD::VP_FSHL; in expandVPFunnelShift() local
7798 ShX = DAG.getNode(ISD::VP_SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt, Mask, in expandVPFunnelShift()
7800 ShY = DAG.getNode(ISD::VP_LSHR, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt, Mask, in expandVPFunnelShift()
7820 if (IsFSHL) { in expandVPFunnelShift()
7851 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift() local
7857 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
7869 if (IsFSHL) { in expandFunnelShift()
7890 ShX = DAG.getNode(ISD::SHL, DL, VT, X, IsFSHL ? ShAmt : InvShAmt); in expandFunnelShift()
7891 ShY = DAG.getNode(ISD::SRL, DL, VT, Y, IsFSHL ? InvShAmt : ShAmt); in expandFunnelShift()
7908 if (IsFSHL) { in expandFunnelShift()