| /freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | IVDescriptors.cpp | 627 RecurrenceDescriptor::InstDesc
641 return InstDesc(false, I); in isAnyOfPattern()
651 return InstDesc(false, I); in isAnyOfPattern()
657 return InstDesc(false, I); in isAnyOfPattern()
663 RecurrenceDescriptor::InstDesc
669 return InstDesc(false, I); in isMinMaxPattern()
683 return InstDesc(false, I); in isMinMaxPattern()
711 return InstDesc(false, I); in isMinMaxPattern()
723 RecurrenceDescriptor::InstDesc
727 return InstDesc(false, I); in isConditionalRdxPattern()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | IVDescriptors.h | 88 class InstDesc {
90 InstDesc(bool IsRecur, Instruction *I, Instruction *ExactFP = nullptr)
94 InstDesc(Instruction *I, RecurKind K, Instruction *ExactFP = nullptr)
126 static InstDesc isRecurrenceInstr(Loop *L, PHINode *Phi, Instruction *I,
127 RecurKind Kind, InstDesc &Prev,
143 static InstDesc isMinMaxPattern(Instruction *I, RecurKind Kind,
144 const InstDesc &Prev);
152 static InstDesc isAnyOfPattern(Loop *Loop, PHINode *OrigPhi, Instruction *I,
153 InstDesc &Prev);
157 static InstDesc isConditionalRdxPattern(RecurKind Kind, Instruction *I);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 161 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
219 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst() argument
224 auto InstID = std::make_pair(InstDesc->getOpcode(), Subtarget); in shouldReplaceInst()
229 unsigned SCIdx = InstDesc->getSchedClass(); in shouldReplaceInst()
257 if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost) in shouldReplaceInst()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 58 uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr,
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| H A D | ARMMCTargetDesc.cpp | 186 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget() argument
191 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8; in evaluateBranchTarget()
198 if (InstDesc.getOpcode() == ARM::tBLXi) in evaluateBranchTarget()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 627 const MCInstrDesc &InstDesc = MI->getDesc(); in tryAddToFoldList() local
628 const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo]; in tryAddToFoldList()
633 for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) { in tryAddToFoldList()
636 !TII->isInlineConstant(Op, InstDesc.operands()[i])) in tryAddToFoldList()
1772 const MCInstrDesc &InstDesc = UseMI->getDesc(); in tryFoldRegSequence() local
1774 TII->getRegClass(InstDesc, OpIdx, TRI, *MI.getMF()); in tryFoldRegSequence()
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| H A D | SIInstrInfo.cpp | 4244 const MCInstrDesc &InstDesc = MI.getDesc(); in isImmOperandLegal() local
4245 const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo]; in isImmOperandLegal()
4266 if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo)) in isImmOperandLegal()
5621 const MCInstrDesc &InstDesc = MI.getDesc(); in isOperandLegal() local
5622 const MCOperandInfo &OpInfo = InstDesc.operands()[OpIdx]; in isOperandLegal()
5651 } else if (AMDGPU::isSISrcOperand(InstDesc, i) && in isOperandLegal()
7664 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitUnaryOp() local
7898 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitBinaryOp() local
8109 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitCountOp() local
8130 BuildMI(MBB, MII, DL, InstDesc, MidReg1).add(SrcRegSub0); in splitScalar64BitCountOp()
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| H A D | GCNHazardRecognizer.cpp | 2850 const MCInstrDesc &InstDesc = I.getDesc(); in fixVALUMaskWriteHazard() local
2851 const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo]; in fixVALUMaskWriteHazard()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 350 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode()); in isMacroFused() local
351 if (!InstDesc.isConditionalBranch()) in isMacroFused()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2158 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); in addLiteralImmOperand() local
2161 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2164 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2165 const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum); in addLiteralImmOperand()
2170 uint8_t OpTy = InstDesc.operands()[OpNum].OperandType; in addLiteralImmOperand()
2187 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
2297 Val = AMDGPU::isSISrcFPOperand(InstDesc, OpNum) ? (uint64_t)Val << 32 in addLiteralImmOperand()
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