4244   const MCInstrDesc &InstDesc = MI.getDesc();  in isImmOperandLegal()  local
4245   const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];  in isImmOperandLegal()
4266   if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))  in isImmOperandLegal()
5621   const MCInstrDesc &InstDesc = MI.getDesc();  in isOperandLegal()  local
5622   const MCOperandInfo &OpInfo = InstDesc.operands()[OpIdx];  in isOperandLegal()
5646             usesConstantBus(MRI, Op, InstDesc.operands().begin()[i])) {  in isOperandLegal()
5651       } else if (AMDGPU::isSISrcOperand(InstDesc, i) &&  in isOperandLegal()
5652                  !isInlineConstant(Op, InstDesc.operands()[i])) {  in isOperandLegal()
7664   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitUnaryOp()  local
7681   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);  in splitScalar64BitUnaryOp()
7687   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);  in splitScalar64BitUnaryOp()
7898   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitBinaryOp()  local
7927   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitBinaryOp()
7932   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitBinaryOp()
8005   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);  in splitScalar64BitBCNT()  local
8021   BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);  in splitScalar64BitBCNT()
8023   BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);  in splitScalar64BitBCNT()
8109   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitCountOp()  local
8130   BuildMI(MBB, MII, DL, InstDesc, MidReg1).add(SrcRegSub0);  in splitScalar64BitCountOp()
8132   BuildMI(MBB, MII, DL, InstDesc, MidReg2).add(SrcRegSub1);  in splitScalar64BitCountOp()