| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 805 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
813 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
821 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
845 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
856 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
873 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
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| H A D | HexagonPatterns.td | 938 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
942 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
952 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
1609 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)),
1613 (Combinew (M2_mpy_up (HiReg $Rss), (HiReg $Rtt)),
1620 (Combinew (Mulhub4 (HiReg $Rss), (HiReg $Rtt)),
1652 (Combinew (Mulhsh2 (HiReg $Rss), (HiReg $Rtt)),
1794 (HiReg $Rss),
1795 (HiReg $Rtt)),
1868 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)),
[all …]
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| H A D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 1129 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
1131 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| H A D | AVRRegisterInfo.cpp | 306 Register &HiReg) const { in splitReg()
310 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 445 Register HiReg, LoReg; in PrintAsmOperand() local
465 HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even); in PrintAsmOperand()
474 Reg = HiReg; in PrintAsmOperand()
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| H A D | SparcISelLowering.cpp | 1322 Register HiReg = VA.getLocReg(); in LowerCall_64() local
1325 HiReg = toCallerWindow(HiReg); in LowerCall_64()
1329 RegsToPass.push_back(std::make_pair(HiReg, Hi64)); in LowerCall_64()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1442 .addReg(HiReg) in selectBallot()
2314 .addReg(HiReg); in selectG_TRUNC()
2317 .addReg(HiReg) in selectG_TRUNC()
2492 .addReg(HiReg) in selectG_SZA_EXT()
2637 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
2642 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg) in selectG_CONSTANT()
2648 .addReg(HiReg) in selectG_CONSTANT()
2706 .addReg(HiReg) in selectG_FNEG()
2748 .addReg(HiReg) in selectG_FABS()
3040 MaskedHi = HiReg; in selectG_PTRMASK()
[all …]
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| H A D | SILoadStoreOptimizer.cpp | 188 Register HiReg; member
1972 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || in computeBase()
1999 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg) in computeBase()
2102 Addr.Base.HiReg = BaseHi.getReg(); in processBaseWithConstOffset()
2149 LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", " in promoteConstantOffsetToImm()
2207 MAddrNext.Base.HiReg != MAddr.Base.HiReg || in promoteConstantOffsetToImm()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 798 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
846 .addReg(HiReg); in expandBuildPairF64()
851 .addReg(HiReg); in expandBuildPairF64()
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| H A D | MipsISelLowering.cpp | 2963 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32() local
2964 assert(HiReg); in CC_MipsO32()
2966 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); in CC_MipsO32()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5486 unsigned LoReg, HiReg; in Select() local
5502 HiReg = X86::EDX; in Select()
5514 HiReg = X86::RDX; in Select()
5591 assert(HiReg && "Register for high half is not defined!"); in Select()
5630 unsigned LoReg, HiReg, ClrReg; in Select() local
5635 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
5639 LoReg = X86::AX; HiReg = X86::DX; in Select()
5644 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; in Select()
5648 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
5745 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) { in Select()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 2048 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
2052 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2054 --HiReg; in CMSEPushCalleeSaves()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 16578 Register HiReg = MI.getOperand(1).getReg(); in emitReadCycleWidePseudo() local
16582 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg) in emitReadCycleWidePseudo()
16593 .addReg(HiReg) in emitReadCycleWidePseudo()
16617 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
16636 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
16657 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
16675 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
17539 Register HiReg = State.AllocateReg(ArgGPRs); in CC_RISCV() local
17540 if (HiReg) { in CC_RISCV()
17542 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); in CC_RISCV()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7358 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
7366 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12826 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
12828 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
12835 .addReg(HiReg) in EmitInstrWithCustomInserter()
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