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Searched refs:FP_TO_SINT (Results 1 – 25 of 40) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2377 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
2378 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
2379 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
2385 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
2386 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
2387 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
2393 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
2394 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
2409 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
2410 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2222 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
2223 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
2349 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, in getCastInstrCost()
2350 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, in getCastInstrCost()
2351 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, in getCastInstrCost()
2352 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, in getCastInstrCost()
2353 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, in getCastInstrCost()
2354 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, in getCastInstrCost()
2355 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, in getCastInstrCost()
2356 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp941 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
1152 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in X86TargetLowering()
1739 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in X86TargetLowering()
2402 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in X86TargetLowering()
20672 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
21136 FpToIntOpcode = ISD::FP_TO_SINT; in LowerFP_TO_INT_SAT()
28781 if (Op->getOpcode() == ISD::FP_TO_SINT || in LowerWin64_FP_TO_INT128()
29143 return DAG.getNode(ISD::FP_TO_SINT, dl, VT, Amt); in convertShiftLeftToScale()
31897 case ISD::FP_TO_SINT: in LowerOperation()
32373 case ISD::FP_TO_SINT: in ReplaceNodeResults()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp707 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
740 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
742 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
744 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
746 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
748 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, in getCastInstrCost()
750 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, in getCastInstrCost()
752 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 }, in getCastInstrCost()
754 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 }, in getCastInstrCost()
756 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp176 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
181 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
460 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
471 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand); in addMVEVectorTypes()
1073 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
5890 if (Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
9710 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
10571 case ISD::FP_TO_SINT: in LowerOperation()
16916 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; in PerformVCVTCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def60 DAG_INSTRUCTION(FPToSI, 1, 0, experimental_constrained_fptosi, FP_TO_SINT)
H A DVPIntrinsics.def461 HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FP_TO_SINT, FPToSI, FP_TO_SINT, 0)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h836 FP_TO_SINT, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp256 setOperationAction(ISD::FP_TO_SINT, T, Custom); in initializeHVXLowering()
329 setOperationAction(ISD::FP_TO_SINT, T, Custom); in initializeHVXLowering()
426 setOperationAction(ISD::FP_TO_SINT, VecTy, Custom); in initializeHVXLowering()
2275 assert(Op.getOpcode() == ISD::FP_TO_SINT || in LowerHvxFpToInt()
2676 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT || in EqualizeFpIntConversion()
2699 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT); in ExpandHvxFpToInt()
2809 if (Opc == ISD::FP_TO_SINT) { in ExpandHvxFpToInt()
3156 case ISD::FP_TO_SINT: in LowerHvxOperation()
3234 case ISD::FP_TO_SINT: in LowerHvxOperation()
3405 case ISD::FP_TO_SINT: in LowerHvxOperationWrapper()
[all …]
H A DHexagonISelLowering.cpp1775 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1776 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1777 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp381 case ISD::FP_TO_SINT: in LegalizeOp()
694 case ISD::FP_TO_SINT: in Promote()
833 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
834 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
H A DLegalizeFloatTypes.cpp925 case ISD::FP_TO_SINT: in SoftenFloatOperand()
1048 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in SoftenFloatOp_FP_TO_XINT()
1901 case ISD::FP_TO_SINT: in ExpandFloatOperand()
2033 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in ExpandFloatOp_FP_TO_XINT()
2232 case ISD::FP_TO_SINT: in PromoteFloatOperand()
3135 case ISD::FP_TO_SINT: in SoftPromoteHalfOperand()
H A DSelectionDAGDumper.cpp369 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
H A DLegalizeDAG.cpp2903 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in PromoteLegalFP_TO_INT()
2919 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
3343 case ISD::FP_TO_SINT: in ExpandNode()
4701 case ISD::FP_TO_SINT: in ConvertNodeToLibcall()
4707 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT || in ConvertNodeToLibcall()
5004 case ISD::FP_TO_SINT: in PromoteNode()
H A DLegalizeIntegerTypes.cpp157 case ISD::FP_TO_SINT: in PromoteIntegerResult()
734 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
735 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
2636 case ISD::FP_TO_SINT: in ExpandIntegerResult()
3731 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in ExpandIntRes_FP_TO_XINT()
3745 Op = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, VT, Op); in ExpandIntRes_FP_TO_XINT()
H A DLegalizeVectorTypes.cpp101 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
682 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
1098 case ISD::FP_TO_SINT: in SplitVectorResult()
3026 case ISD::FP_TO_SINT: in SplitVectorOperand()
4242 case ISD::FP_TO_SINT: in WidenVectorResult()
6072 case ISD::FP_TO_SINT: in WidenVectorOperand()
H A DTargetLowering.cpp8116 ISD::FP_TO_SINT; in expandFP_TO_UINT()
8134 Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); in expandFP_TO_UINT()
8181 SInt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val); in expandFP_TO_UINT()
8190 SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); in expandFP_TO_UINT()
8192 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, in expandFP_TO_UINT()
10763 SDValue FpToInt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, in expandFP_TO_INT_SAT()
10786 DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, DstVT, Src); in expandFP_TO_INT_SAT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp110 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64}, in R600TargetLowering()
201 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
595 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1739 case ISD::FP_TO_SINT: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp438 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
458 setOperationAction({ISD::ADD, ISD::AND, ISD::FP_TO_SINT, in AMDGPUTargetLowering()
1362 case ISD::FP_TO_SINT: in LowerOperation()
1888 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
3038 SDValue IntE = DAG.getNode(ISD::FP_TO_SINT, SL, MVT::i32, E); in lowerFEXP()
3448 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
3603 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT()
3608 return LowerFP_TO_INT64(Op, DAG, OpOpcode == ISD::FP_TO_SINT); in LowerFP_TO_INT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp274 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in PPCTargetLowering()
275 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, in PPCTargetLowering()
531 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
541 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
686 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
727 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
8195 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in convertFPToInt()
8249 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INTForReuse()
8306 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
11763 case ISD::FP_TO_SINT: in ReplaceNodeResults()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1689 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1691 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
3261 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3612 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3618 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp80 setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom); in LoongArchTargetLowering()
127 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in LoongArchTargetLowering()
270 setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal); in LoongArchTargetLowering()
316 setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal); in LoongArchTargetLowering()
399 case ISD::FP_TO_SINT: in LowerOperation()
1837 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp885 case ISD::FP_TO_SINT: in getCastInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp521 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()
697 ISD::MULHU, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in NVPTXTargetLowering()
781 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
2714 case ISD::FP_TO_SINT: in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp357 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
368 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
1248 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2802 if (Val.getOpcode() != ISD::FP_TO_SINT || in lowerFP_TO_SINT_STORE()

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