Lines Matching refs:FP_TO_SINT
176 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
181 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
460 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
471 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand); in addMVEVectorTypes()
951 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
952 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); in ARMTargetLowering()
1002 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1073 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
1075 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
5890 if (Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
5910 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT in LowerFP_TO_INT()
9710 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
9749 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
9862 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
10571 case ISD::FP_TO_SINT: in LowerOperation()
16916 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; in PerformVCVTCombine()
18894 case ISD::FP_TO_SINT: in PerformDAGCombine()