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Searched refs:FNEG (Results 1 – 25 of 48) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1538 if (Val.getOpcode() == ISD::FNEG) in peekFNeg()
1545 if (Val.getOpcode() == ISD::FNEG) in peekFPSignOps()
4498 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
4550 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
4712 if (LHS.getOpcode() != ISD::FNEG) in performFNegCombine()
4717 if (RHS.getOpcode() != ISD::FNEG) in performFNegCombine()
4736 if (LHS.getOpcode() == ISD::FNEG) in performFNegCombine()
4738 else if (RHS.getOpcode() == ISD::FNEG) in performFNegCombine()
4761 if (LHS.getOpcode() == ISD::FNEG) in performFNegCombine()
4768 if (RHS.getOpcode() != ISD::FNEG) in performFNegCombine()
[all …]
H A DAMDGPUISelDAGToDAG.cpp2794 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3ModsImpl()
2853 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
2923 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
2935 if (Lo.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
2940 if (Hi.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
3123 if (ModOpcode == ISD::FNEG) { in selectWMMAModsNegAbs()
3175 if (Element.getOpcode() != ISD::FNEG) in SelectWMMAModsF16Neg()
3195 if (ElV2f16.getOpcode() != ISD::FNEG) in SelectWMMAModsF16Neg()
3224 ModOpcode = (ElF16.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS; in SelectWMMAModsF16NegAbs()
3245 ModOpcode = (ElV2f16.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS; in SelectWMMAModsF16NegAbs()
[all …]
H A DSIISelLowering.cpp229 setOperationAction(ISD::FNEG, MVT::bf16, Expand); in SITargetLowering()
747 setOperationAction(ISD::FNEG, MVT::v2f16, Legal); in SITargetLowering()
5597 case ISD::FNEG: in LowerOperation()
6025 case ISD::FNEG: { in ReplaceNodeResults()
10292 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in lowerFastUnsafeFDIV()
10321 SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y); in lowerFastUnsafeFDIV64()
10471 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, in LowerFDIV32()
10824 DAG.getNode(ISD::FNEG, DL, VT, SqrtSNextDown, Flags); in lowerFSQRTF32()
12386 case ISD::FNEG: in isCanonicalized()
13086 if ((Vec.getOpcode() == ISD::FNEG || in performExtractVectorEltCombine()
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H A DR600Instructions.td688 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
691 "FNEG $dst, $src0",
1208 def FNEG_R600 : FNEG<R600_Reg32>;
H A DAMDGPUTargetTransformInfo.cpp676 case ISD::FNEG: in getArithmeticInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def111 ADD_UNARY_VVP_OP(VVP_FNEG, FNEG) HANDLE_VP_TO_VVP(VP_FNEG, VVP_FNEG) REGISTER_PACKED(VVP_FNEG)
H A DVVPInstrPatternsVec.td134 /// FNEG {
179 /// } FNEG
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h928 FNEG, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp15078 FPOpcode = ISD::FNEG; in foldBitcastedFPLogic()
15232 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
15251 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
15925 ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
15939 if (matcher.match(N00, ISD::FNEG)) { in visitFSUBForFMACombine()
15945 ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
15961 if (matcher.match(N0, ISD::FNEG)) { in visitFSUBForFMACombine()
15969 ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
16109 matcher.getNode(ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
16765 return DAG.getNode(ISD::FNEG, DL, VT, in visitFMUL()
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H A DLegalizeFloatTypes.cpp105 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; in SoftenFloatResult()
1334 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1427 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1601 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1602 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
2413 case ISD::FNEG: in PromoteFloatResult()
2821 case ISD::FNEG: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp383 case ISD::FNEG: in LegalizeOp()
946 case ISD::FNEG: in Expand()
1692 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
H A DSelectionDAGBuilder.h535 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } in visitFNeg()
H A DLegalizeDAG.cpp1638 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) { in ExpandFCOPYSIGN()
1640 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue); in ExpandFCOPYSIGN()
3530 case ISD::FNEG: in ExpandNode()
3678 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) { in ExpandNode()
3680 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); in ExpandNode()
4279 SDValue Neg = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(2), Flags); in ExpandNode()
5361 case ISD::FNEG: in PromoteNode()
H A DSelectionDAGDumper.cpp200 case ISD::FNEG: return "fneg"; in getOperationName()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1108 { ISD::FNEG, MVT::v4f64, { 1, 1, 1, 2 } }, // vxorpd in getArithmeticInstrCost()
1109 { ISD::FNEG, MVT::v8f32, { 1, 1, 1, 2 } }, // vxorps in getArithmeticInstrCost()
1209 { ISD::FNEG, MVT::v4f64, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
1210 { ISD::FNEG, MVT::v8f32, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
1347 { ISD::FNEG, MVT::f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1348 { ISD::FNEG, MVT::f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1349 { ISD::FNEG, MVT::v4f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1350 { ISD::FNEG, MVT::v2f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1373 { ISD::FNEG, MVT::f32, { 2, 2, 1, 2 } }, // Pentium III from http://www.agner.org/ in getArithmeticInstrCost()
1415 { ISD::FNEG, MVT::f64, { 2, 2, 1, 3 } }, // (x87) in getArithmeticInstrCost()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1804 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1911 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1914 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1933 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
2930 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
3074 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3291 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
612 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
1117 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>;
H A DAArch64SchedCyclone.td436 // FABS,FNEG are WriteF
H A DAArch64SchedExynosM3.td545 def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td161 defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td190 (instregex "FNEG(D|S)$"),
1057 (instregex "FNEG(D|S)_rec$"),
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def334 VP_PROPERTY_FUNCTIONAL_SDOPC(FNEG)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td120 defm FNEG : FT_XZ<0b000111, "fneg", UnOpFrag<(fneg node:$Src)>>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1331 case ISD::FNEG: { in getArithmeticInstrCost()
H A DRISCVISelLowering.cpp448 ISD::FNEG, ISD::STRICT_FMA, ISD::STRICT_FADD, in RISCVTargetLowering()
916 ISD::FABS, ISD::FNEG, ISD::FCOPYSIGN, ISD::FCEIL, in RISCVTargetLowering()
1292 ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FSQRT, in RISCVTargetLowering()
5588 OP_CASE(FNEG) in getRISCVVLOp()
5612 VP_CASE(FNEG) // VP_FNEG in getRISCVVLOp()
6567 case ISD::FNEG: in LowerOperation()
15179 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
15188 if (Op0.getOpcode() == ISD::FNEG) { in PerformDAGCombine()
15253 if (Op0.getOpcode() == ISD::FNEG) in PerformDAGCombine()
15534 if (In2.getOpcode() != ISD::FNEG) in PerformDAGCombine()
[all …]

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