Searched refs:ElementWidth (Results 1 – 6 of 6) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 381 int ElementWidth; member 406 unsigned ElementWidth; member 419 unsigned ElementWidth; member 1287 if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth)) in isSVEPredicateVectorRegOfWidth() 1298 if (isSVEPredicateAsCounterReg<Class>() && (Reg.ElementWidth == ElementWidth)) in isSVEPredicateAsCounterRegOfWidth() 1309 if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth) in isSVEDataVectorRegOfWidth() 1417 if (VectorList.ElementWidth != ElementWidth) in isTypedVectorList() 2264 Op->Reg.ElementWidth = ElementWidth; in CreateVectorReg() 2277 Op->VectorList.ElementWidth = ElementWidth; in CreateVectorList() 2322 if (ElementWidth == 64) in ComputeRegsForAlias() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1006 class PPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass { 1007 let Name = "SVEPredicateList" # NumRegs # "x" # ElementWidth; 1010 # NumRegs #", 0, "#ElementWidth #">"; 1036 class PPRVectorListMul<int ElementWidth, int NumRegs> : PPRVectorList<ElementWidth, NumRegs> { 1037 let Name = "SVEPredicateListMul" # NumRegs # "x" # ElementWidth; 1165 let Name = "SVEVectorList" # NumRegs # ElementWidth; 1261 class ZPRVectorListMul<int ElementWidth, int NumRegs> : ZPRVectorList<ElementWidth, NumRegs> { 1262 let Name = "SVEVectorListMul" # NumRegs # "x" # ElementWidth; 1371 class ZPRVectorListStrided<int ElementWidth, int NumRegs, int Stride> 1372 : ZPRVectorList<ElementWidth, NumRegs> { [all …]
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| H A D | SVEInstrFormats.td | 208 class SVEShiftedImmOperand<int ElementWidth, string Infix, string Predicate> 210 let Name = "SVE" # Infix # "Imm" # ElementWidth; 227 class imm8_opt_lsl<int ElementWidth, string printType, 231 let DecoderMethod = "DecodeImm8OptLsl<" # ElementWidth # ">";
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 288 template <int ElementWidth> 2017 template <int ElementWidth> 2022 if (ElementWidth == 8 && Shift) in DecodeImm8OptLsl()
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| /freebsd-14.2/contrib/llvm-project/clang/lib/AST/ |
| H A D | ExprConstant.cpp | 7364 CharUnits ElementWidth = Info.Ctx.getTypeSizeInChars(Ty->getElementType()); in visit() local 7369 visitType(Ty->getElementType(), Offset + I * ElementWidth); in visit()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8421 const unsigned ElementWidth = 8; in lowerGetVectorLength() local 8424 unsigned LMul1VF = RISCV::RVVBitsPerBlock / ElementWidth; in lowerGetVectorLength() 8436 unsigned VSEW = RISCVVType::encodeSEW(ElementWidth); in lowerGetVectorLength()
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