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Searched refs:EXTRACT_SUBVECTOR (Results 1 – 25 of 29) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1449 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
2858 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, Expanded, in SplitVecRes_VECTOR_SPLICE()
2861 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, Expanded, in SplitVecRes_VECTOR_SPLICE()
2908 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, Load, in SplitVecRes_VP_REVERSE()
2911 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, Load, in SplitVecRes_VP_REVERSE()
3314 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
5591 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR) in isSETCCorConvertedSETCC()
6278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Res, in WidenVecOp_Convert()
6322 ISD::EXTRACT_SUBVECTOR, dl, DstVT, Res, in WidenVecOp_FP_TO_XINT_SAT()
6454 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), in WidenVecOp_EXTRACT_SUBVECTOR()
[all …]
H A DDAGCombiner.cpp722 case ISD::EXTRACT_SUBVECTOR: in getStoreSource()
2043 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
19936 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
20133 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
23256 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
23597 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
23976 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
24260 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && in foldExtractSubvectorFromShuffleVector()
24517 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT, in visitEXTRACT_SUBVECTOR()
24582 ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, in visitEXTRACT_SUBVECTOR()
[all …]
H A DLegalizeIntegerTypes.cpp115 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
502 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
1550 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); in PromoteIntRes_TRUNCATE()
1823 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
5575 SDValue Step1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NInVT, InOp0, in PromoteIntRes_EXTRACT_SUBVECTOR()
5579 ISD::EXTRACT_SUBVECTOR, dl, OutVT, Step1, in PromoteIntRes_EXTRACT_SUBVECTOR()
5587 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), OutVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
5602 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
5915 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
H A DSelectionDAGDumper.cpp305 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
H A DSelectionDAG.cpp2816 case ISD::EXTRACT_SUBVECTOR: { in isSplatValue()
3222 case ISD::EXTRACT_SUBVECTOR: { in computeKnownBits()
4716 case ISD::EXTRACT_SUBVECTOR: { in ComputeNumSignBits()
5499 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR || in foldCONCAT_VECTORS()
6905 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
6933 case ISD::EXTRACT_SUBVECTOR: { in getNode()
11621 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) in peekThroughExtractSubvectors()
11975 return getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op, in matchBinOpReduction()
12030 if (Op0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
12031 Op1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
[all …]
H A DSelectionDAGBuilder.cpp430 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, PartEVT, Val, in getCopyFromPartsVector()
808 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, in getCopyToPartsVector()
3921 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result, in visitShuffleVector()
3966 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src, in visitShuffleVector()
7699 DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index)); in visitIntrinsicCall()
11924 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
11926 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h573 EXTRACT_SUBVECTOR, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4723 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && in LowerMUL()
4725 N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in LowerMUL()
4777 ISD::EXTRACT_SUBVECTOR, DL, OVT, in LowerMUL()
5884 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
5888 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
6222 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
18497 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR && in tryExtendDUPToExtractHigh()
18539 if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR) in isEssentiallyExtractHighSubvector()
19223 if (Op1.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performSVEMulAddSubCombine()
23903 case ISD::EXTRACT_SUBVECTOR: in PerformDAGCombine()
[all …]
H A DAArch64ISelDAGToDAG.cpp166 if (N->getOpcode() != ISD::EXTRACT_SUBVECTOR || in SelectExtractHigh()
4245 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && "Invalid Node!"); in trySelectCastScalableToFixedLengthVector()
4426 case ISD::EXTRACT_SUBVECTOR: { in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h461 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in LoHalf()
472 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in HiHalf()
H A DHexagonISelLoweringHVX.cpp134 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
234 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
391 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1600 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubTy, in extractSubvector()
3133 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RetTy, in WidenHvxSetCC()
3208 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelDAGToDAG.cpp925 case ISD::EXTRACT_SUBVECTOR: return SelectHvxExtractSubvector(N); in Select()
941 case ISD::EXTRACT_SUBVECTOR: return SelectExtractSubvector(N); in Select()
H A DHexagonISelLowering.cpp1644 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1693 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3347 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp2809 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SingleTy, FoldedShuff, in ppHvxShuffleOfShuffle()
2816 if (V.getOpcode() != ISD::EXTRACT_SUBVECTOR) in ppHvxShuffleOfShuffle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp254 case ISD::EXTRACT_SUBVECTOR: in getIdiomaticVectorType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3530 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Vec, in lowerBuildVectorOfConstants()
3649 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, in lowerBuildVectorOfConstants()
3718 Splat = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, in lowerBuildVectorOfConstants()
4104 if (V1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in isDeinterleaveShuffle()
4105 V2.getOpcode() != ISD::EXTRACT_SUBVECTOR) in isDeinterleaveShuffle()
4318 while (Parent.getOpcode() == ISD::EXTRACT_SUBVECTOR && in lowerVECTOR_SHUFFLEAsVSlidedown()
4370 ISD::EXTRACT_SUBVECTOR, DL, VT, in lowerVECTOR_SHUFFLEAsVSlidedown()
4616 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, in lowerBitreverseShuffle()
6406 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
9845 ISD::EXTRACT_SUBVECTOR, DL, VecVT, Interleaved, in lowerVECTOR_INTERLEAVE()
[all …]
H A DRISCVISelDAGToDAG.cpp2047 case ISD::EXTRACT_SUBVECTOR: { in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2438 ISD::EXTRACT_SUBVECTOR, in X86TargetLowering()
3765 if (LHS.getOpcode() != ISD::EXTRACT_SUBVECTOR || in getSplitVectorSrc()
3766 RHS.getOpcode() != ISD::EXTRACT_SUBVECTOR || in getSplitVectorSrc()
4857 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in getTargetConstantBitsFromNode()
4981 if (V.getOpcode() == ISD::EXTRACT_SUBVECTOR && in IsNOT()
6315 if (Opcode == ISD::EXTRACT_SUBVECTOR) { in getShuffleScalarElt()
12307 if (N0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in lowerShuffleOfExtractsAsVperm()
12308 N1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in lowerShuffleOfExtractsAsVperm()
12397 case ISD::EXTRACT_SUBVECTOR: { in lowerShuffleAsBroadcast()
50722 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && in isHorizontalBinOp()
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H A DX86ISelLowering.h1252 Op.getOpcode() == ISD::EXTRACT_SUBVECTOR || in isTargetCanonicalConstantNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp176 ISD::EXTRACT_SUBVECTOR}); in WebAssemblyTargetLowering()
2519 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorExtendCombine()
2701 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, VecIdx); in extractSubVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp187 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
444 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addMVEVectorTypes()
6223 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
9769 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9771 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9773 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9775 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9806 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
9808 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
10144 Pred = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MemVT, Pred, in LowerPredicateLoad()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp393 ISD::EXTRACT_SUBVECTOR, in AMDGPUTargetLowering()
1337 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
1718 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in splitVector()
1721 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL, in splitVector()
1814 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
H A DSIISelLowering.cpp336 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
631 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
1869 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
1958 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, in convertArgType()
6982 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE()
7365 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT, in constructRetValue()
7865 auto Subvector = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp, in lowerSBuffer()
9148 : DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, in getMemIntrinsicNode()
9163 SDValue Value = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Op, in getMemIntrinsicNode()
12444 case ISD::EXTRACT_SUBVECTOR: { in isCanonicalized()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td754 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
762 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2688 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()

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