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Searched refs:DstRB (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp716 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping() local
718 if (!DstRB) in getInstrMapping()
719 DstRB = SrcRB; in getInstrMapping()
721 SrcRB = DstRB; in getInstrMapping()
724 assert(DstRB && SrcRB && "Both RegBank were nullptr"); in getInstrMapping()
727 DefaultMappingID, copyCost(*DstRB, *SrcRB, TypeSize::getFixed(Size)), in getInstrMapping()
728 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
741 const RegisterBank &DstRB = in getInstrMapping() local
746 DefaultMappingID, copyCost(DstRB, SrcRB, TypeSize::getFixed(Size)), in getInstrMapping()
747 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
H A DAArch64InstructionSelector.cpp3181 if (DstRB.getID() != SrcRB.getID()) { in select()
3187 if (DstRB.getID() == AArch64::GPRRegBankID) { in select()
3219 } else if (DstRB.getID() == AArch64::FPRRegBankID) { in select()
4048 getRegClassForTypeOnBank(ScalarTy, DstRB, true); in emitExtractVectorElt()
4149 const RegisterBank &DstRB = in selectSplitVectorUnmerge() local
5897 const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI); in tryOptBuildVecToSubregToReg() local
5898 if (EltRB != DstRB) in tryOptBuildVecToSubregToReg()
5909 getRegClassForTypeOnBank(MRI.getType(Dst), DstRB); in tryOptBuildVecToSubregToReg()
7737 const RegisterBank *DstRB = MRI.getRegBankOrNull(DstReg); in fixupPHIOpBanks() local
7747 if (RB != DstRB) { in fixupPHIOpBanks()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp301 if (DstRB->getID() != AMDGPU::SGPRRegBankID && in selectG_AND_OR_XOR()
302 DstRB->getID() != AMDGPU::VCCRegBankID) in selectG_AND_OR_XOR()
2254 const RegisterBank *DstRB; in selectG_TRUNC() local
2258 DstRB = SrcRB; in selectG_TRUNC()
2260 DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_TRUNC()
2261 if (SrcRB != DstRB) in selectG_TRUNC()
2560 if (DstRB->getID() != AMDGPU::SGPRRegBankID) in selectG_FPEXT()
2601 if (DstRB->getID() == AMDGPU::VCCRegBankID) { in selectG_CONSTANT()
2676 if (DstRB->getID() != AMDGPU::SGPRRegBankID || in selectG_FNEG()
2722 if (DstRB->getID() != AMDGPU::SGPRRegBankID || in selectG_FABS()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp228 const RegisterBank &DstRB = DstIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping() local
232 MappingID, Cost, getCopyMapping(DstRB.getID(), SrcRB.getID(), DstSize), in getInstrMapping()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp768 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt() local
771 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
777 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
789 if (DstRB.getID() != X86::GPRRegBankID) in selectTruncOrPtrToInt()
897 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext() local
900 assert(DstRB.getID() == SrcRB.getID() && in selectAnyext()
906 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
915 if (DstRB.getID() != X86::GPRRegBankID) in selectAnyext()
1135 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectUAddSub() local
1136 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectUAddSub()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1124 const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI); in verifyPreISelGenericInstruction() local
1127 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) { in verifyPreISelGenericInstruction()