300   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_AND_OR_XOR()  local
301   if (DstRB->getID() != AMDGPU::SGPRRegBankID &&  in selectG_AND_OR_XOR()
302       DstRB->getID() != AMDGPU::VCCRegBankID)  in selectG_AND_OR_XOR()
305   bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID &&  in selectG_AND_OR_XOR()
327   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_ADD_SUB()  local
328   const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID;  in selectG_ADD_SUB()
1501   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectGroupStaticSize()  local
1502   unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ?  in selectGroupStaticSize()
2254   const RegisterBank *DstRB;  in selectG_TRUNC()  local
2258     DstRB = SrcRB;  in selectG_TRUNC()
2260     DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_TRUNC()
2261     if (SrcRB != DstRB)  in selectG_TRUNC()
2265   const bool IsVALU = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_TRUNC()
2273       TRI.getRegClassForSizeOnBank(DstSize, *DstRB);  in selectG_TRUNC()
2559   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);  in selectG_FPEXT()  local
2560   if (DstRB->getID() != AMDGPU::SGPRRegBankID)  in selectG_FPEXT()
2597   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_CONSTANT()  local
2598   const bool IsSgpr = DstRB->getID() == AMDGPU::SGPRRegBankID;  in selectG_CONSTANT()
2601   if (DstRB->getID() == AMDGPU::VCCRegBankID) {  in selectG_CONSTANT()
2675   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);  in selectG_FNEG()  local
2676   if (DstRB->getID() != AMDGPU::SGPRRegBankID ||  in selectG_FNEG()
2721   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);  in selectG_FABS()  local
2722   if (DstRB->getID() != AMDGPU::SGPRRegBankID ||  in selectG_FABS()
2939   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_GLOBAL_VALUE()  local
2940   const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_GLOBAL_VALUE()
2958   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_PTRMASK()  local
2961   const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_PTRMASK()
2962   if (DstRB != SrcRB) // Should only happen for hand written MIR.  in selectG_PTRMASK()
2988   const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB);  in selectG_PTRMASK()
3097   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_EXTRACT_VECTOR_ELT()  local
3109       TRI.getRegClassForTypeOnBank(DstTy, *DstRB);  in selectG_EXTRACT_VECTOR_ELT()
3502   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectWaveAddress()  local
3503   const bool IsVALU = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectWaveAddress()