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Searched refs:DestVT (Results 1 – 24 of 24) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1203 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1211 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1744 MVT DestVT = VA.getValVT(); in selectRet() local
1746 if (RVVT != DestVT) { in selectRet()
1776 EVT SrcVT, DestVT; in selectTrunc() local
1782 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in selectTrunc()
1814 MVT DestVT = DestEVT.getSimpleVT(); in selectIntExt() local
1859 if ((DestVT != MVT::i32) && (DestVT != MVT::i16)) in emitIntSExt()
1894 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) || in emitIntExt()
1914 MVT DestVT = DestEVT.getSimpleVT(); in selectDivRem() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1273 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1441 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1447 ArgVT = DestVT; in processCallArgs()
1453 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1459 ArgVT = DestVT; in processCallArgs()
1508 MVT DestVT = VA.getValVT(); in finishCall() local
1509 MVT CopyVT = DestVT; in finishCall()
1760 if (RVVT != DestVT) { in SelectRet()
1809 if (DestVT != MVT::i32 && DestVT != MVT::i64) in PPCEmitIntExt()
1829 } else if (DestVT == MVT::i32) { in PPCEmitIntExt()
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H A DPPCISelLowering.h1025 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
H A DPPCISelLowering.cpp9116 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
9117 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
9125 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
9126 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
9127 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
9135 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
9136 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
9137 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
17211 bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
17212 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFree()
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/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp299 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
300 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n"; in EmitAction()
301 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
313 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
314 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; in EmitAction()
315 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2822 MVT DestVT; in selectFPToInt() local
2823 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt()
2855 MVT DestVT; in selectIntToFP() local
2862 assert((DestVT == MVT::f32 || DestVT == MVT::f64) && in selectIntToFP()
3953 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 && in selectTrunc()
4001 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 || in emiti1Ext()
4005 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emiti1Ext()
4398 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && in emitIntExt()
4399 (DestVT != MVT::i32) && (DestVT != MVT::i64)) || in emitIntExt()
4434 if (DestVT == MVT::i8 || DestVT == MVT::i16) in emitIntExt()
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H A DAArch64ISelLowering.cpp11183 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
11190 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
11210 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
11216 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
11221 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
11224 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
11235 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1741 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp()
1953 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1956 ArgVT = DestVT; in ProcessCallArgs()
1962 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1965 ArgVT = DestVT; in ProcessCallArgs()
2128 MVT DestVT = VA.getValVT(); in SelectRet() local
2130 if (RVVT != DestVT) { in SelectRet()
2588 EVT SrcVT, DestVT; in SelectTrunc() local
2594 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectTrunc()
2608 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) in ARMEmitIntExt()
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H A DARMISelLowering.cpp8259 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
8267 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8283 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8289 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8294 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8297 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8300 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const;
191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const;
H A DVECustomDAG.cpp480 SDValue VECustomDAG::getUnpack(EVT DestVT, SDValue Vec, PackElem Part, in getUnpack() argument
487 return DAG.getNode(OC, DL, DestVT, Vec, AVL); in getUnpack()
490 SDValue VECustomDAG::getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, in getPack() argument
495 return DAG.getNode(VEISD::VEC_PACK, DL, DestVT, LoVec, HiVec, AVL); in getPack()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp890 EVT DestVT = Node->getValueType(0); in LegalizeLoadOps() local
1773 (SlotVT.bitsLT(DestVT) && in EmitStackConvert()
1800 if (SlotVT.bitsEq(DestVT)) in EmitStackConvert()
2624 EVT DestVT = Node->getValueType(0); in ExpandLegalINT_TO_FP() local
2633 (DestVT.bitsLE(MVT::f64) || in ExpandLegalINT_TO_FP()
2636 DestVT))) { in ExpandLegalINT_TO_FP()
2809 if (DestVT == MVT::f32) in ExpandLegalINT_TO_FP()
2844 EVT DestVT = N->getValueType(0); in PromoteLegalINT_TO_FP() local
2890 DAG.getNode(OpToUse, dl, DestVT, in PromoteLegalINT_TO_FP()
2905 EVT DestVT = N->getValueType(0); in PromoteLegalFP_TO_INT() local
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H A DSelectionDAGBuilder.cpp3648 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitZExt() local
3658 TLI.isSExtCheaperThanZExt(N.getValueType(), DestVT)) { in visitZExt()
3680 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitFPTrunc() local
3681 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N, in visitFPTrunc()
3736 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT); in visitPtrToInt()
3748 N = DAG.getPtrExtOrTrunc(N, getCurSDLoc(), DestVT); in visitIntToPtr()
3760 if (DestVT != N.getValueType()) in visitBitCast()
3762 DestVT, N)); // convert types. in visitBitCast()
6670 EVT DestVT = TLI.getValueType(DLayout, I.getType()); in visitIntrinsicCall() local
8158 EVT DestVT = TLI.getValueType(DLayout, VPIntrin.getType()); in visitVectorPredicationIntrinsic() local
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H A DLegalizeTypes.cpp896 EVT DestVT) { in CreateStackStoreLoad() argument
903 Align DestAlign = DAG.getReducedAlign(DestVT, /*UseABI=*/false); in CreateStackStoreLoad()
912 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align); in CreateStackStoreLoad()
H A DLegalizeTypes.h219 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
H A DLegalizeVectorTypes.cpp422 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local
440 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags()); in ScalarizeVecRes_UnaryOp()
2385 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local
2387 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp()
2403 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2583 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
2589 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
2591 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
2594 MVT DestVT) { in setOperationPromotedToType() argument
2597 AddPromotedToType(Op, OrigVT, DestVT); in setOperationPromotedToType()
3062 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
3063 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
3080 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
3081 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
3083 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3308 if (DestVT == MVT::f16) in LowerUINT_TO_FP()
3317 if (DestVT == MVT::bf16) { in LowerUINT_TO_FP()
3339 if (DestVT == MVT::f32) in LowerUINT_TO_FP()
3342 assert(DestVT == MVT::f64); in LowerUINT_TO_FP()
3354 if (DestVT == MVT::f16) in LowerSINT_TO_FP()
3363 if (DestVT == MVT::bf16) { in LowerSINT_TO_FP()
3388 if (DestVT == MVT::f32) in LowerSINT_TO_FP()
3391 assert(DestVT == MVT::f64); in LowerSINT_TO_FP()
3594 if (DestVT != MVT::i64) in LowerFP_TO_INT()
5006 if (DestVT.isVector()) { in PerformDAGCombine()
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H A DAMDGPUISelLowering.h204 bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override;
H A DSIISelLowering.h290 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
H A DSIISelLowering.cpp962 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
965 DestVT.getScalarType() == MVT::f32 && in isFPExtFoldable()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1190 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local
1191 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1192 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1193 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); in getVectorTypeBreakdownMVT()
1671 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local
1672 RegisterVT = DestVT; in getVectorTypeBreakdown()
1674 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1679 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1374 bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override;
H A DX86ISelLowering.cpp18935 MVT DestVT = Cast.getSimpleValueType(); in vectorizeExtractedCast() local
18945 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM); in vectorizeExtractedCast()
18965 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast, in vectorizeExtractedCast()
24306 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT; in LowerEXTEND_VECTOR_INREG() local
24308 unsigned DestWidth = DestVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG()
24310 unsigned DestElts = DestVT.getVectorNumElements(); in LowerEXTEND_VECTOR_INREG()
24319 Curr = DAG.getBitcast(DestVT, Curr); in LowerEXTEND_VECTOR_INREG()
24322 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()
33831 bool X86TargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable()
33833 return !(SrcVT == MVT::i32 && DestVT == MVT::i16); in isNarrowingProfitable()