Home
last modified time | relevance | path

Searched refs:CreateReg (Results 1 – 25 of 75) sorted by relevance

123

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixVGPRCopies.cpp64 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp212 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
219 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp636 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
684 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
795 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
844 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
850 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
863 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
869 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
897 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
1287 SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg( in lowerDbgValue()
1311 Op = MachineOperand::CreateReg(Reg, false); in lowerDbgDeclare()
[all …]
H A DFunctionLoweringInfo.cpp364 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() function in FunctionLoweringInfo
385 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTOCRegDeps.cpp121 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
H A DPPCPreEmitPeephole.cpp339 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
341 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp241 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
252 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
263 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
371 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
387 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
H A DMachineOutliner.cpp953 MachineOperand::CreateReg(I, true, /* isDef = true */ in outline()
959 MachineOperand::CreateReg(I, false, /* isDef = false */ in outline()
H A DMachineInstr.cpp89 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true)); in addImplicitDefUseOperands()
91 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true)); in addImplicitDefUseOperands()
1983 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
2049 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
2086 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp217 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
H A DARMBaseInstrInfo.h547 MachineOperand::CreateReg(PredReg, false)}};
553 return MachineOperand::CreateReg(CCReg, false);
560 return MachineOperand::CreateReg(ARM::CPSR,
H A DThumb2InstrInfo.cpp583 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
615 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
H A DARMSLSHardening.cpp353 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertIndirectCallToIndirectJump()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertReadWriteCSR.cpp81 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in INITIALIZE_PASS()
H A DRISCVInsertWriteVXRM.cpp383 MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false, in emitWriteVXRM()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp470 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); in changeToAddrMode()
473 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h212 Register CreateReg(MVT VT, bool isDivergent = false);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp200 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anonb0eaffc40111::MSP430Operand
454 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); in ParseOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp213 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anonca5d59280111::AVROperand
415 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc())); in tryParseRegisterOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp599 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anonb0359a6c0211::VEOperand
1475 Operands.push_back(VEOperand::CreateReg(Reg1, S1, E1)); in parseOperand()
1476 Operands.push_back(VEOperand::CreateReg(Reg2, S2, E2)); in parseOperand()
1533 Op = VEOperand::CreateReg(Reg, S, E); in parseVEAsmOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp84 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
90 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp373 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false)); in addNodeIDRegType()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SLSHardening.cpp370 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertBLRToBL()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3169 Operands.push_back(AArch64Operand::CreateReg( in tryParseSyspXzrPair()
4575 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
4590 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
4605 Operands.push_back(AArch64Operand::CreateReg( in tryParseZTOperand()
4644 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
4659 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
6208 Operands[2] = AArch64Operand::CreateReg( in MatchAndEmitInstruction()
6371 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
6387 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
6404 Operands[1] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
[all …]

123