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Searched refs:CondCodes (Results 1 – 25 of 42) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.h33 enum CondCodes { enum
71 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
72 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
73 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
H A DAVRInstrInfo.cpp195 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const { in getBrCond()
218 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const { in getCondFromBranchOpc()
241 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const { in getOppositeCondition()
323 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); in analyzeBranch()
385 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
420 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
473 AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp67 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
136 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
186 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg); in MoveCopyOutOfITBlock()
202 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
225 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
243 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg); in InsertITInstructions()
H A DARMLoadStoreOptimizer.cpp489 ARMCC::CondCodes Pred, in UpdateBaseRegUses()
630 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
908 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); in MergeOpsUpdate()
1297 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in MergeBaseUpdateLSMultiple()
1493 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in MergeBaseUpdateLoadStore()
1631 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSDouble()
1801 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in FixInvalidRegPairOp()
1881 ARMCC::CondCodes CurrPred = ARMCC::AL; in LoadStoreMultipleOpti()
2171 ARMCC::CondCodes &Pred, bool &isT2);
2256 Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) { in CanFormLdStDWord()
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H A DARMBaseInstrInfo.h165 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
167 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() in getPredicate()
544 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
785 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
801 ARMCC::CondCodes Pred, Register PredReg,
808 ARMCC::CondCodes Pred, Register PredReg,
H A DThumbRegisterInfo.h42 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
H A DThumb2InstrInfo.h78 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
H A DARMInstructionSelector.cpp54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
391 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
393 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL}; in getComparePreds()
575 ARMCC::CondCodes Cond, in insertComparison()
H A DMLxExpansionPass.cpp281 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
H A DThumbRegisterInfo.cpp65 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
85 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
H A DThumb2SizeReduction.cpp187 bool is2Addr, ARMCC::CondCodes Pred,
331 bool is2Addr, ARMCC::CondCodes Pred, in VerifyPredAndCC()
801 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
893 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
H A DARMBaseRegisterInfo.h213 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
H A DARMBaseRegisterInfo.cpp499 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
850 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateFrameIndex()
851 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in eliminateFrameIndex()
H A DThumb2InstrInfo.cpp74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
293 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate()
766 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI, in getITInstrPredicate()
H A DARMBaseInstrInfo.cpp217 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm(); in convertToThreeAddress()
553 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); in reverseBranchCondition()
597 CC += ARMCondCodeToString((ARMCC::CondCodes)Op.getImm()); in createMIROperandComment()
640 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); in SubsumesPredicate()
641 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); in SubsumesPredicate()
2241 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in getInstrPredicate()
2264 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
2842 inline static ARMCC::CondCodes getCmpToAddCondition(ARMCC::CondCodes CC) { in getCmpToAddCondition()
3159 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> in optimizeCompareInstr()
3180 ARMCC::CondCodes CC; in optimizeCompareInstr()
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H A DMVETPAndVPTOptimisationsPass.cpp574 static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) { in GetCondCode()
576 return ARMCC::CondCodes(Instr.getOperand(3).getImm()); in GetCondCode()
593 ARMCC::CondCodes ExpectedCode = GetCondCode(Cond); in IsVPNOTEquivalent()
H A DARMBlockPlacement.cpp280 MIB.addImm(ARMCC::CondCodes::AL); in moveBasicBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Utils/
H A DARMBaseInfo.h30 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
48 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
71 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { in getSwappedCondition()
146 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
219 MSP430CC::CondCodes BranchCode = in analyzeBranch()
220 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in analyzeBranch()
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
H A DMSP430.h22 enum CondCodes { enum
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparc.h41 enum CondCodes { enum
105 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
H A DSparcInstrInfo.cpp84 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition()
396 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm()); in reverseBranchCondition()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTX.h28 enum CondCodes { enum
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp975 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printPredicateOperand()
986 if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS) in printMandatoryRestrictedPredicateOperand()
996 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryPredicateOperand()
1004 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryInvertedPredicateOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp214 O << SPARCCondCodeToString((SPCC::CondCodes)CC); in printCCOperand()

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