175                            ARMCC::CondCodes Pred, unsigned PredReg);
179         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
185         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
489                                         ARMCC::CondCodes Pred,  in UpdateBaseRegUses()
630     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreMulti()
837     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreDouble()
908   ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);  in MergeOpsUpdate()
1191                                   ARMCC::CondCodes Pred, Register PredReg) {  in isIncrementOrDecrement()
1223                  ARMCC::CondCodes Pred, Register PredReg, int &Offset) {  in findIncDecBefore()
1243                 ARMCC::CondCodes Pred, Register PredReg, int &Offset,  in findIncDecAfter()
1297   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLSMultiple()
1493   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLoadStore()
1631   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in MergeBaseUpdateLSDouble()
1736                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,  in InsertLDR_STR()
1801   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in FixInvalidRegPairOp()
1881   ARMCC::CondCodes CurrPred = ARMCC::AL;  in LoadStoreMultipleOpti()
1901       ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);  in LoadStoreMultipleOpti()
2171                           ARMCC::CondCodes &Pred, bool &isT2);
2256     Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {  in CanFormLdStDWord()
2416         ARMCC::CondCodes Pred = ARMCC::AL;  in RescheduleOps()