| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 621 const SrcOp &CarryIn) { in buildUAdde() argument
623 {Op0, Op1, CarryIn}); in buildUAdde()
629 const SrcOp &CarryIn) { in buildUSube() argument
631 {Op0, Op1, CarryIn}); in buildUSube()
637 const SrcOp &CarryIn) { in buildSAdde() argument
639 {Op0, Op1, CarryIn}); in buildSAdde()
645 const SrcOp &CarryIn) { in buildSSube() argument
647 {Op0, Op1, CarryIn}); in buildSSube()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 362 auto CarryIn = InvertCarryFlag(Subtarget, CurDAG, Dl, Op2); in selectSubCarry() local
365 Dl, {Type0, Type1}, {Op0, Op1, CarryIn}); in selectSubCarry()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 880 MachineOperand *CarryIn = TII->getNamedOperand(MISucc, AMDGPU::OpName::src2); in pseudoOpConvertToVOP2() local
881 if (!CarryIn) in pseudoOpConvertToVOP2()
886 if (!MRI->hasOneUse(CarryIn->getReg()) || !MRI->use_empty(CarryOut->getReg())) in pseudoOpConvertToVOP2()
911 MISucc.substituteRegister(CarryIn->getReg(), TRI->getVCC(), 0, *TRI); in pseudoOpConvertToVOP2()
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| H A D | AMDGPULegalizerInfo.cpp | 3813 [&](Register &LocalAccum, const Carry &CarryIn) -> Register { in buildMultiply() argument
3814 if (CarryIn.empty()) in buildMultiply()
3819 if (CarryIn.size() == 1) { in buildMultiply()
3821 LocalAccum = B.buildZExt(S32, CarryIn[0]).getReg(0); in buildMultiply()
3827 CarryAccum = B.buildZExt(S32, CarryIn[0]).getReg(0); in buildMultiply()
3828 for (unsigned i = 1; i + 1 < CarryIn.size(); ++i) { in buildMultiply()
3830 B.buildUAdde(S32, S1, CarryAccum, getZero32(), CarryIn[i]) in buildMultiply()
3841 B.buildUAdde(S32, S1, CarryAccum, LocalAccum, CarryIn.back()); in buildMultiply()
3868 (!UsePartialMad64_32 || !CarryIn.empty())) { in buildMultiply()
3880 if (CarryIn.empty()) { in buildMultiply()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVPseudos.td | 1512 bit CarryIn,
1516 !if(CarryIn,
1536 bit CarryIn,
1540 !if(CarryIn,
2445 // For vadc and vsbc, CarryIn == 1 and CarryOut == 0
2451 def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
2453 !if(!and(CarryIn, !not(CarryOut)),
2467 def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
2469 !if(!and(CarryIn, !not(CarryOut)),
2497 def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorCombine.cpp | 465 Value *CarryIn = nullptr) const
1938 Value *CarryIn) const in createAddCarry()
1945 if (CarryIn == nullptr && HVC.HST.useHVXV66Ops()) { in createAddCarry()
1949 if (CarryIn == nullptr) in createAddCarry()
1950 CarryIn = HVC.getNullValue(HVC.getBoolTy(HVC.length(VecTy))); in createAddCarry()
1951 Args.push_back(CarryIn); in createAddCarry()
1964 if (CarryIn != nullptr) { in createAddCarry()
1974 {CarryIn, HVC.getConstInt(Mask)}); in createAddCarry()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2121 std::optional<Register> CarryIn; in widenScalarAddSubOverflow() local
2144 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2149 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2154 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2159 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2167 if (CarryIn) in widenScalarAddSubOverflow()
2179 if (CarryIn) { in widenScalarAddSubOverflow()
5565 Register CarryDst, CarryIn; in narrowScalarAddSub() local
5569 CarryIn = MI.getOperand(NumDefs + 2).getReg(); in narrowScalarAddSub()
5594 if (!CarryIn) { in narrowScalarAddSub()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 3383 SDValue CarryIn = N->getOperand(2); in visitADDE() local
3402 SDValue CarryIn = N->getOperand(2); in visitUADDO_CARRY() local
3412 if (isNullConstant(CarryIn)) { in visitUADDO_CARRY()
3440 SDValue Ops[] = {N1, N0, CarryIn}; in visitUADDO_CARRY()
3606 CarryIn = getAsCarry(TLI, CarryIn, true); in combineCarryDiamond()
3607 if (!CarryIn) in combineCarryDiamond()
3689 SDValue CarryIn = N->getOperand(2); in visitSADDO_CARRY() local
3699 if (isNullConstant(CarryIn)) { in visitSADDO_CARRY()
4297 SDValue CarryIn = N->getOperand(2); in visitSUBE() local
4312 if (isNullConstant(CarryIn)) { in visitUSUBO_CARRY()
[all …]
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| H A D | TargetLowering.cpp | 10392 SDValue CarryIn = DAG.getConstant(0, dl, Node->getValueType(1)); in expandUADDSUBO() local
10394 { LHS, RHS, CarryIn }); in expandUADDSUBO()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 535 Value *CarryIn = II.getArgOperand(0); in simplifyX86addcarry() local
545 if (match(CarryIn, PatternMatch::m_ZeroInt())) { in simplifyX86addcarry()
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| H A D | X86ISelLowering.cpp | 54008 SDValue CarryIn = N->getOperand(2); in combineADC() local
54015 CarryIn); in combineADC()
54030 DAG.getTargetConstant(X86::COND_B, DL, MVT::i8), CarryIn), in combineADC()
54043 DAG.getConstant(Sum, DL, LHS.getValueType()), CarryIn); in combineADC()
54046 if (SDValue Flags = combineCarryThroughADD(CarryIn, DAG)) { in combineADC()
54057 LHS.getOperand(1), CarryIn); in combineADC()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2656 SDValue CarryIn = N->getOperand(FirstInputOp + 2); in SelectMVE_VADCSBC() local
2657 ConstantSDNode *CarryInConstant = dyn_cast<ConstantSDNode>(CarryIn); in SelectMVE_VADCSBC()
2664 Ops.push_back(CarryIn); in SelectMVE_VADCSBC()
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