Lines Matching refs:CarryIn
2121 std::optional<Register> CarryIn; in widenScalarAddSubOverflow() local
2144 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2149 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2154 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2159 CarryIn = MI.getOperand(4).getReg(); in widenScalarAddSubOverflow()
2167 if (CarryIn) in widenScalarAddSubOverflow()
2179 if (CarryIn) { in widenScalarAddSubOverflow()
2183 {LHSExt, RHSExt, *CarryIn}) in widenScalarAddSubOverflow()
3745 auto [Res, CarryOut, LHS, RHS, CarryIn] = MI.getFirst5Regs(); in lower()
3756 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); in lower()
3763 auto Carry2 = MIRBuilder.buildAnd(CondTy, ResEqZero, CarryIn); in lower()
5565 Register CarryDst, CarryIn; in narrowScalarAddSub() local
5569 CarryIn = MI.getOperand(NumDefs + 2).getReg(); in narrowScalarAddSub()
5594 if (!CarryIn) { in narrowScalarAddSub()
5599 {Src1Regs[i], Src2Regs[i], CarryIn}); in narrowScalarAddSub()
5602 {Src1Regs[i], Src2Regs[i], CarryIn}); in narrowScalarAddSub()
5606 CarryIn = CarryOut; in narrowScalarAddSub()