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Searched refs:CPSR (Results 1 – 25 of 36) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h122 MIB.addReg(ARM::CPSR, RegState::Define);
130 MIB.addReg(ARM::CPSR);
158 MIB.addReg(ARM::CPSR);
186 MIB.addReg(ARM::CPSR);
H A DThumb2SizeReduction.cpp256 return is_contained(MCID.implicit_defs(), ARM::CPSR); in HasImplicitCPSRDef()
302 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
382 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
816 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
880 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
907 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
984 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
999 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
1045 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR); in ReduceMBB()
1100 if (BundleMI->killsRegister(ARM::CPSR)) in ReduceMBB()
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H A DARMInstrThumb.td419 let Defs = [CPSR];
968 let isCommutable = 1, Uses = [CPSR] in
1007 let isCommutable = 1, Uses = [CPSR] in
1104 let isCompare = 1, Defs = [CPSR] in {
1119 } // isCompare = 1, Defs = [CPSR]
1122 let isCompare = 1, Defs = [CPSR] in {
1151 } // isCompare = 1, Defs = [CPSR]
1229 let Defs = [CPSR] in
1310 let Uses = [CPSR] in
1356 /// instruction modifies the CPSR register.
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H A DThumb1InstrInfo.cpp60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
64 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
H A DARMFastISel.cpp252 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
253 *CPSR = true; in DefinesOptionalPredicate()
290 bool CPSR = false; in AddOptionalDefs() local
291 if (DefinesOptionalPredicate(MI, &CPSR)) in AddOptionalDefs()
292 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
1254 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1277 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1480 .addImm(ARMPred).addReg(ARM::CPSR); in SelectCmp()
1664 .addReg(ARM::CPSR); in SelectSelect()
1672 .addReg(ARM::CPSR); in SelectSelect()
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H A DARMBaseInstrInfo.cpp765 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
984 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
987 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
2266 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
3123 if (Instr.modifiesRegister(ARM::CPSR, TRI) || in optimizeCompareInstr()
3124 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
3268 if (Succ->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
3288 MI->clearRegisterDeads(ARM::CPSR); in optimizeCompareInstr()
4401 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
5606 if (CmpMI->modifiesRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
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H A DARMInstrInfo.td85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
1889 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1892 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1905 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1959 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
3726 let Uses = [CPSR] in
3734 let Defs = [CPSR] in {
3894 // CPSR and the implicit def of CPSR is not needed.
5026 Defs = [CPSR] in {
5837 let Defs = [CPSR] in
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H A DThumbRegisterInfo.cpp186 auto isCpsr = [](auto &MO) { return MO.getReg() == ARM::CPSR; }; in emitThumbRegPlusImmInReg()
201 auto liveOutIsCpsr = [](auto &Out) { return Out.PhysReg == ARM::CPSR; }; in emitThumbRegPlusImmInReg()
214 .addReg(ARM::CPSR, RegState::Implicit); in emitThumbRegPlusImmInReg()
H A DARMInstrThumb2.td726 /// changed to modify CPSR.
1027 let Defs = [CPSR], Uses = [CPSR], hasPostISelHook = PostISelHook in {
1031 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
1041 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
1055 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
2487 // CPSR and the implicit def of CPSR is not needed.
2794 let Uses = [CPSR] in {
2962 /// changed to modify CPSR.
4549 let Defs = [CPSR] in
4585 let Defs = [CPSR] in
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H A DARM.td393 /// Some instructions update CPSR partially, which can add false dependency for
395 /// mapped to a separate physical register. Avoid partial CPSR update for these
398 /// that partially update CPSR and add false dependency on the previous
399 /// CPSR setting instruction.
402 "Avoid CPSR partial update for OOO execution">;
404 /// Disable +1 predication cost for instructions updating CPSR.
406 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
410 "Disable +1 predication cost for instructions updating CPSR">;
H A DThumb2ITBlockPass.cpp172 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
H A DARMInstructionSelector.cpp602 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
796 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1136 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
H A DARMExpandPseudoInsts.cpp1192 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1316 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1857 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1881 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1974 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1980 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2002 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2340 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2542 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2754 .addReg(ARM::CPSR, RegState::Undef) in ExpandMI()
H A DARMAsmPrinter.cpp1865 .addReg(ARM::CPSR) in emitInstruction()
1921 .addReg(ARM::CPSR) in emitInstruction()
2052 .addReg(ARM::CPSR) in emitInstruction()
2071 .addReg(ARM::CPSR) in emitInstruction()
2086 .addReg(ARM::CPSR) in emitInstruction()
H A DMVETPAndVPTOptimisationsPass.cpp200 MIB.addReg(ARM::CPSR, RegState::Define); in RevertWhileLoopSetup()
209 MIB.addReg(ARM::CPSR); in RevertWhileLoopSetup()
H A DARMLowOverheadLoops.cpp1454 RDA->isSafeToDefRegAt(MI, MCRegister::from(ARM::CPSR), Ignore); in RevertLoopDec()
1484 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
1495 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
H A DARMISelLowering.cpp11050 .addReg(ARM::CPSR); in EmitSjLjDispatchBlock()
11105 .addReg(ARM::CPSR); in EmitSjLjDispatchBlock()
11206 .addReg(ARM::CPSR); in EmitSjLjDispatchBlock()
11728 .addReg(ARM::CPSR, in EmitLowered__chkstk()
11744 .addReg(ARM::CPSR, in EmitLowered__chkstk()
11787 .addReg(ARM::CPSR); in EmitLowered__dbzchk()
11805 if (mi.readsRegister(ARM::CPSR)) in checkAndUpdateCPSRKill()
11815 if (Succ->isLiveIn(ARM::CPSR)) in checkAndUpdateCPSRKill()
12168 copy0MBB->addLiveIn(ARM::CPSR); in EmitInstrWithCustomInserter()
12169 sinkMBB->addLiveIn(ARM::CPSR); in EmitInstrWithCustomInserter()
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H A DThumb1FrameLowering.cpp463 .addDef(ARM::CPSR) in emitPrologue()
469 .addDef(ARM::CPSR) in emitPrologue()
H A DARMRegisterInfo.td184 def CPSR : ARMReg<0, "cpsr">;
394 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
H A DARMBaseInstrInfo.h560 return MachineOperand::CreateReg(ARM::CPSR,
H A DThumb2InstrInfo.cpp555 !MI.definesRegister(ARM::CPSR)) { in rewriteT2FrameIndex()
H A DARMLoadStoreOptimizer.cpp211 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
639 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) == in CreateLoadStoreMulti()
3179 if (Increment->definesRegister(ARM::CPSR) || in DistributeIncrements()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp179 if (MO.isReg() && MO.getReg() == ARM::CPSR && in isCPSRDefined()
245 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, in initLLVMToCVRegMapping()
H A DARMMCCodeEmitter.cpp313 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue()
714 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { in HasConditionalBranch()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2473 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
10182 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10232 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10239 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10285 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10293 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10681 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
10914 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) in checkTargetMatchPredicate()
10918 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && in checkTargetMatchPredicate()
10921 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
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