4830     SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,  in getARMCmp()
4987   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSignedALUO()
5132     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSELECT()
5531     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSELECT_CC()
5566   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSELECT_CC()
5673       SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in OptimizeVFPBrcond()
5722     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerBRCOND()
5776     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerBR_CC()
5785     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerBR_CC()
5802   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerBR_CC()
6314   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerShiftRightParts()
6358   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerShiftLeftParts()
6966   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSETCCCARRY()
6967   SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,  in LowerSETCCCARRY()
10530   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerFSETCC()
10865         .addReg(ARM::CPSR, RegState::Define)  in SetupEntryBlockForSjLj()
10870         .addReg(ARM::CPSR, RegState::Define)  in SetupEntryBlockForSjLj()
11050       .addReg(ARM::CPSR);  in EmitSjLjDispatchBlock()
11105       .addReg(ARM::CPSR);  in EmitSjLjDispatchBlock()
11109         .addReg(ARM::CPSR, RegState::Define)  in EmitSjLjDispatchBlock()
11121         .addReg(ARM::CPSR, RegState::Define)  in EmitSjLjDispatchBlock()
11141           .addReg(ARM::CPSR, RegState::Define)  in EmitSjLjDispatchBlock()
11206       .addReg(ARM::CPSR);  in EmitSjLjDispatchBlock()
11651     MIB->getOperand(5).setReg(ARM::CPSR);  in EmitStructByval()
11656       .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);  in EmitStructByval()
11728         .addReg(ARM::CPSR,  in EmitLowered__chkstk()
11744         .addReg(ARM::CPSR,  in EmitLowered__chkstk()
11787       .addReg(ARM::CPSR);  in EmitLowered__dbzchk()
11805     if (mi.readsRegister(ARM::CPSR))  in checkAndUpdateCPSRKill()
11807     if (mi.definesRegister(ARM::CPSR))  in checkAndUpdateCPSRKill()
11815       if (Succ->isLiveIn(ARM::CPSR))  in checkAndUpdateCPSRKill()
11821   SelectItr->addRegisterKilled(ARM::CPSR, TRI);  in checkAndUpdateCPSRKill()
12166     if (!MI.killsRegister(ARM::CPSR) &&  in EmitInstrWithCustomInserter()
12168       copy0MBB->addLiveIn(ARM::CPSR);  in EmitInstrWithCustomInserter()
12169       sinkMBB->addLiveIn(ARM::CPSR);  in EmitInstrWithCustomInserter()
12225         .addImm(ARMCC::EQ).addReg(ARM::CPSR);  in EmitInstrWithCustomInserter()
12235         .addImm(ARMCC::EQ).addReg(ARM::CPSR);  in EmitInstrWithCustomInserter()
12244       .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);  in EmitInstrWithCustomInserter()
12319       .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);  in EmitInstrWithCustomInserter()
12452     if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {  in AdjustInstrPostInstrSelection()
12476   MO.setReg(ARM::CPSR);  in AdjustInstrPostInstrSelection()
18474       SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,  in PerformCMOVCombine()
18488       SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,  in PerformCMOVCombine()
20481     return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);  in getRegForInlineAsmConstraint()