| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.h | 42 class AllocationOrder; variable 331 const AllocationOrder &Order); 342 MCRegister tryAssign(const LiveInterval &, AllocationOrder &, 344 MCRegister tryEvict(const LiveInterval &, AllocationOrder &, 347 MCRegister tryRegionSplit(const LiveInterval &, AllocationOrder &, 351 AllocationOrder &Order, 357 AllocationOrder &Order, 366 AllocationOrder &Order); 374 unsigned tryBlockSplit(const LiveInterval &, AllocationOrder &, 378 unsigned tryLocalSplit(const LiveInterval &, AllocationOrder &, [all …]
|
| H A D | AllocationOrder.h | 30 class LLVM_LIBRARY_VISIBILITY AllocationOrder { 45 const AllocationOrder &AO; 49 Iterator(const AllocationOrder &AO, int Pos) : AO(AO), Pos(Pos) {} in Iterator() 84 static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM, 90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() function
|
| H A D | AllocationOrder.cpp | 29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create() 52 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
|
| H A D | RegAllocEvictionAdvisor.h | 21 class AllocationOrder; variable 108 const LiveInterval &VirtReg, const AllocationOrder &Order, 129 const AllocationOrder &Order, 211 const AllocationOrder &, uint8_t,
|
| H A D | RegisterScavenging.cpp | 130 const LiveRegUnits &LiveOut, ArrayRef<MCPhysReg> AllocationOrder, in findSurvivorBackwards() argument 152 for (MCPhysReg Reg : AllocationOrder) { in findSurvivorBackwards() 177 for (MCPhysReg Reg : AllocationOrder) { in findSurvivorBackwards() 305 ArrayRef<MCPhysReg> AllocationOrder = RC.getRawAllocationOrder(MF); in scavengeRegisterBackwards() local 307 *MRI, std::prev(MBBI), To, LiveUnits, AllocationOrder, RestoreAfter); in scavengeRegisterBackwards()
|
| H A D | RegAllocGreedy.cpp | 400 AllocationOrder &Order, in tryAssign() 534 const AllocationOrder &Order, in getOrderLimit() 580 AllocationOrder &Order, in tryEvict() 1063 AllocationOrder &Order, in tryRegionSplit() 1097 AllocationOrder &Order, in calculateRegionSplitCostAroundReg() 1174 AllocationOrder &Order, in calculateRegionSplitCost() 1236 AllocationOrder &Order) { in trySplitAroundHintReg() 1296 AllocationOrder &Order, in tryBlockSplit() 1417 AllocationOrder &Order, in tryInstructionSplit() 1570 AllocationOrder &Order, in tryLocalSplit() [all …]
|
| H A D | RegAllocFast.cpp | 911 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg() local 912 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg() 966 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef() local 967 assert(!AllocationOrder.empty() && "Allocation order must not be empty"); in allocVirtRegUndef() 968 PhysReg = AllocationOrder[0]; in allocVirtRegUndef() 1044 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in defineVirtReg() local 1045 if (AllocationOrder.empty()) in defineVirtReg() 1047 return setPhysReg(MI, MO, *AllocationOrder.begin()); in defineVirtReg() 1135 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg() local 1136 if (AllocationOrder.empty()) in useVirtReg() [all …]
|
| H A D | MLRegAllocEvictAdvisor.cpp | 307 const AllocationOrder &Order, 323 const LiveInterval &VirtReg, const AllocationOrder &Order, 439 const LiveInterval &VirtReg, const AllocationOrder &Order, 588 const LiveInterval &, const AllocationOrder &, unsigned, uint8_t, in tryFindEvictionCandidatePosition() argument 664 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() 1085 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition()
|
| H A D | RegAllocEvictionAdvisor.cpp | 276 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
|
| H A D | RegAllocBasic.cpp | 266 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.td | 480 // Make AllocationOrder as similar as G8RC's to avoid potential spilling.
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.td | 87 // or AllocationOrder
|
| /freebsd-14.2/lib/clang/libllvm/ |
| H A D | Makefile | 190 SRCS_MIN+= CodeGen/AllocationOrder.cpp
|