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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
52 def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2),
56 def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2),
78 def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2),
82 def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2),
86 def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2),
90 def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2),
100 def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2),
118 def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2),
1999 def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
13 (MI HvxVR:$src1, IntRegs:$src2)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
28 (MI HvxVR:$src1, HvxVR:$src2)>;
32 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
33 (MI HvxWR:$src1, HvxWR:$src2)>;
35 (MI HvxWR:$src1, HvxWR:$src2)>;
86 (MI HvxQR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td119 (MI HvxWR:$src1, IntRegs:$src2)>;
127 (MI HvxVR:$src1, IntRegs:$src2)>;
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132 (MI HvxWR:$src1, HvxVR:$src2)>;
135 (MI HvxWR:$src1, HvxVR:$src2)>;
139 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
143 (MI HvxWR:$src1, HvxWR:$src2)>;
147 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
151 (MI HvxVR:$src1, HvxVR:$src2)>;
163 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
[all …]
H A DHexagonIntrinsics.td135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
136 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
138 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
207 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
289 def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
299 def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
301 (SUB_64_VAL u3_64_ImmPred:$src2))>,
323 (MI HvxVR:$src1, HvxVR:$src2,
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrXOP.td174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
251 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
259 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrAMX.td85 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
89 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
93 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
97 "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
133 u8imm:$src2, u8imm:$src3),
135 timm:$src2, timm:$src3)]>;
137 u8imm:$src2, u8imm:$src3),
139 timm:$src2, timm:$src3)]>;
141 u8imm:$src2, u8imm:$src3),
145 u8imm:$src2, u8imm:$src3),
[all …]
H A DX86InstrSSE.td28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
51 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
58 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
81 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
237 def : InstAlias<OpcodeStr#".s\t{$src2, $dst|$dst, $src2}",
5627 "vptest\t{$src2, $src1|$src1, $src2}",
5649 "ptest\t{$src2, $src1|$src1, $src2}",
5653 "ptest\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrFMA.td42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
83 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
184 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
192 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
205 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
404 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrShiftRotate.td35 "shl{b}\t{$src2, $dst|$dst, $src2}",
39 "shl{w}\t{$src2, $dst|$dst, $src2}",
43 "shl{l}\t{$src2, $dst|$dst, $src2}",
48 "shl{q}\t{$src2, $dst|$dst, $src2}",
138 "shr{b}\t{$src2, $dst|$dst, $src2}",
141 "shr{w}\t{$src2, $dst|$dst, $src2}",
145 "shr{l}\t{$src2, $dst|$dst, $src2}",
149 "shr{q}\t{$src2, $dst|$dst, $src2}",
240 "sar{b}\t{$src2, $dst|$dst, $src2}",
243 "sar{w}\t{$src2, $dst|$dst, $src2}",
[all …]
H A DX86InstrKL.td21 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
22 "loadiwkey\t{$src2, $src1|$src1, $src2}",
23 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
42 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
44 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
48 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
50 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
54 "aesenc256kl\t{$src2, $src1|$src1, $src2}",
56 (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8XS,
60 "aesdec256kl\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrCMovSetCC.td21 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
27 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
33 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
42 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
43 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
47 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
48 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
52 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
[all …]
H A DX86InstrArithmetic.td155 "imul{w}\t{$src2, $dst|$dst, $src2}",
160 "imul{l}\t{$src2, $dst|$dst, $src2}",
166 "imul{q}\t{$src2, $dst|$dst, $src2}",
175 "imul{w}\t{$src2, $dst|$dst, $src2}",
181 "imul{l}\t{$src2, $dst|$dst, $src2}",
187 "imul{q}\t{$src2, $dst|$dst, $src2}",
645 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
679 mnemonic, "{$src2, $dst|$dst, $src2}", []>,
695 mnemonic, "{$src2, $src1|$src1, $src2}", []>,
708 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
[all …]
H A DX86InstrCompiler.td677 "{$src2, $dst|$dst, $src2}"),
684 "{$src2, $dst|$dst, $src2}"),
692 "{$src2, $dst|$dst, $src2}"),
700 "{$src2, $dst|$dst, $src2}"),
709 "{$src2, $dst|$dst, $src2}"),
717 "{$src2, $dst|$dst, $src2}"),
725 "{$src2, $dst|$dst, $src2}"),
733 "{$src2, $dst|$dst, $src2}"),
740 "{$src2, $dst|$dst, $src2}"),
748 "{$src2, $dst|$dst, $src2}"),
[all …]
H A DX86InstrAVX512.td1705 OpcodeStr, "$src3, $src2", "$src2, $src3",
4585 "$src2, $src1", "$src1, $src2",
5444 "$src2, $src1", "$src1, $src2",
5584 "$src2, $src1", "$src1, $src2",
5589 "$src2, $src1", "$src1, $src2",
5606 "$src2, $src1", "$src1, $src2",
5611 "$src2, $src1", "$src1, $src2",
6209 "$src2, $src1", "$src1, $src2",
6215 "$src2, $src1", "$src1, $src2",
11672 "$src3, $src2", "$src2, $src3",
[all …]
H A DX86InstrMMX.td39 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
46 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
57 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
62 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
67 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
527 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrMPX.td30 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
31 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
33 def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
34 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
37 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
38 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
40 def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
41 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
H A DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
27 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
28 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
30 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
H A DX86InstrVecCompiler.td401 (ANDPSrm VR128:$src1, f128mem:$src2)>;
404 (ANDPSrr VR128:$src1, VR128:$src2)>;
407 (ORPSrm VR128:$src1, f128mem:$src2)>;
410 (ORPSrr VR128:$src1, VR128:$src2)>;
413 (XORPSrm VR128:$src1, f128mem:$src2)>;
416 (XORPSrr VR128:$src1, VR128:$src2)>;
422 (VANDPSrm VR128:$src1, f128mem:$src2)>;
425 (VANDPSrr VR128:$src1, VR128:$src2)>;
428 (VORPSrm VR128:$src1, f128mem:$src2)>;
431 (VORPSrr VR128:$src1, VR128:$src2)>;
[all …]
/freebsd-13.1/contrib/cortex-strings/src/arm/
H A Dstrcmp.S82 #define src2 r1 macro
165 ldrb r3, [src2]
176 orr tmp1, src1, src2
194 bic src2, src2, #7
285 bic src2, src2, #3
298 sub src2, src2, tmp1
324 add src2, src2, #4
352 add src2, src2, #4
361 bic src2, src2, #3
428 ldrh data2, [src2]
[all …]
/freebsd-13.1/contrib/sendmail/libsm/
H A Db-strcmp.c56 char src1[SIZE], src2[SIZE]; local
88 (void) sm_strlcpy(src2, "1234567890", SIZE);
92 (void) sm_strlcpy(src2, "1234567891", SIZE);
96 (void) sm_strlcpy(src2, "1234567891", SIZE);
100 k, src1, src2);
108 j += strcasecmp(src1, src2);
119 j += sm_strcasecmp(src1, src2);
H A Dstrl.c148 sm_strlcat2(dst, src1, src2, len) in sm_strlcat2() argument
151 register const char *src2;
161 return o + strlen(src1) + strlen(src2);
174 return j + strlen(src1 + i) + strlen(src2);
180 for (i = 0; i < len && (dst[j] = src2[i]) != 0; i++, j++)
183 if (src2[i] == '\0')
186 return j + strlen(src2 + i);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td228 // src1 = Denominator, src2 = Numerator).
234 // Denominator, src2 = Numerator).
323 SDTCisSameAs<4, 2>, // f32 src2
395 [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
396 (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
399 [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
435 [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
447 [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
451 [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
467 [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
[all …]
/freebsd-13.1/contrib/cortex-strings/src/aarch64/
H A Dmemcmp.S44 #define src2 x1 macro
65 eor tmp1, src1, src2
75 ldr data2, [src2], #8
126 bic src2, src2, #7
131 ldr data2, [src2], #8
156 ldrb data2w, [src2], #1
H A Dstrcmp.S46 #define src2 x1 macro
65 eor tmp1, src1, src2
76 ldr data2, [src2], #8
141 bic src2, src2, #7
145 ldr data2, [src2], #8
161 ldrb data2w, [src2], #1
/freebsd-13.1/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h253 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbssd_internal() argument
254 return __builtin_ia32_tdpbssd_internal(m, n, k, dst, src1, src2); in _tile_dpbssd_internal()
260 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbsud_internal() argument
261 return __builtin_ia32_tdpbsud_internal(m, n, k, dst, src1, src2); in _tile_dpbsud_internal()
267 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbusd_internal() argument
268 return __builtin_ia32_tdpbusd_internal(m, n, k, dst, src1, src2); in _tile_dpbusd_internal()
274 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbuud_internal() argument
275 return __builtin_ia32_tdpbuud_internal(m, n, k, dst, src1, src2); in _tile_dpbuud_internal()
289 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbf16ps_internal() argument
290 return __builtin_ia32_tdpbf16ps_internal(m, n, k, dst, src1, src2); in _tile_dpbf16ps_internal()

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