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/freebsd-13.1/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h152 __builtin_ia32_tdpbssd((dst), (src0), (src1))
171 __builtin_ia32_tdpbsud((dst), (src0), (src1))
190 __builtin_ia32_tdpbusd((dst), (src0), (src1))
209 __builtin_ia32_tdpbuud((dst), (src0), (src1))
227 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
362 dst->tile = _tile_dpbssd_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbssd()
363 src0.tile, src1.tile); in __tile_dpbssd()
385 dst->tile = _tile_dpbsud_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbsud()
408 dst->tile = _tile_dpbusd_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbusd()
431 dst->tile = _tile_dpbuud_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbuud()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td188 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
191 // out = (src1 > src0) ? 1 : 0
252 // src0: vec4(src, 0, 0, mask)
321 // i32 or f32 src0
387 [(int_amdgcn_ldexp node:$src0, node:$src1),
388 (AMDGPUldexp_impl node:$src0, node:$src1)]>;
391 [(int_amdgcn_class node:$src0, node:$src1),
392 (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
415 [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
439 [(int_amdgcn_mul_u24 node:$src0, node:$src1),
[all …]
H A DSIInstructions.td59 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
69 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
1684 (i32 (sext i1:$src0)),
1690 (i32 (ext i1:$src0)),
1984 (S_NOT_B64 $src0)
1989 (S_NOT_B64 $src0)
2023 (S_NOT_B32 $src0)
2028 (S_NOT_B32 $src0)
2337 (COPY $src0)
2385 (COPY $src0)
[all …]
H A DAMDGPUInstructions.td160 (ops node:$src0),
161 (op $src0),
170 (ops node:$src0, node:$src1),
171 (op $src0, $src1),
180 (op $src0, $src1, $src2),
189 (op $src0, $src1),
241 (ops node:$src0), (srl_oneuse node:$src0, (i32 16))
246 (ops node:$src0), (i16 (trunc (i32 (srl_16 node:$src0))))
610 (dt rc:$src0)
623 (BIT_ALIGN $src0, $src0, $src1)
[all …]
H A DSOPInstructions.td77 bits<8> src0;
101 "$src0", pattern> {
118 "$src0", pattern> {
156 opName, (outs), (ins rc:$src0), "$src0", pattern> {
397 bits<8> src0;
429 (ops node:$src0),
430 (Op $src0),
442 (Op $src0, $src1),
642 "$src0, $src1"
656 "$src0, $src1"
[all …]
H A DEvergreenInstructions.td495 (fcopysign f32:$src0, f32:$src1),
500 (fcopysign f32:$src0, f64:$src1),
506 (fcopysign f64:$src0, f64:$src1),
508 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
515 (fcopysign f64:$src0, f32:$src1),
517 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
536 (fshr i32:$src0, i32:$src1, i32:$src2),
537 (BIT_ALIGN_INT_eg $src0, $src1, $src2)
591 let src0 = 0;
804 def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
[all …]
H A DR600Instructions.td447 (ins i32imm:$src0),
448 "INTERP_LOAD $src0 : $dst">;
695 (ins rc:$src0),
696 "FABS $dst, $src0",
702 (ins rc:$src0),
703 "FNEG $dst, $src0",
1091 (ins R600_Reg128:$src0),
1092 "CUBE $dst $src0",
1229 (fdiv f32:$src0, f32:$src1),
1731 (cnd $src0, $src1, $src2)
[all …]
H A DVOP3Instructions.td14 dag src0 = !if(P.HasOMod,
19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
226 let Ins64 = (ins InterpSlot:$src0,
316 // result = src0 * src1 + src2
323 // result = src0 * src1 + src2
533 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
549 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
622 // to the new src0.
775 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
[all …]
H A DVOP2Instructions.td15 bits<9> src0;
27 bits<9> src0;
598 (Inst $src0, $src1),
599 (Inst $src1, $src0)
607 (Inst $src0, $src1, 0),
608 (Inst $src1, $src0, 0)
805 (inst $src0, $src1), sub0,
819 (and vt:$src0, vt:$src1),
824 (or vt:$src0, vt:$src1),
829 (xor vt:$src0, vt:$src1),
[all …]
H A DVOPInstructions.td188 bits<9> src0;
271 let Inst{49-41} = src0;
284 let Inst{49-41} = src0;
292 bits<9> src0;
316 bits<9> src0;
350 bits<10> src0;
415 bits<8> src0;
451 bits<9> src0; // {src0_sgpr{0}, src0{7-0}}
605 bits<8> src0;
722 bits<8> src0;
[all …]
H A DAMDGPUGISel.td228 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
229 (inst src0_vt:$src0, src1_vt:$src1)
238 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
239 (inst src0_vt:$src0, src1_vt:$src1)
248 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
249 (inst src0_vt:$src0, src1_vt:$src1)
258 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
259 (inst src0_vt:$src0, src1_vt:$src1)
268 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
269 (inst src0_vt:$src1, src1_vt:$src0)
[all …]
H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
36 : EXPCommon<done, "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")
99 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
102 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
108 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
110 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
H A DVOP3PInstructions.td23 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
104 (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)),
123 (mixlo_inst $src0_modifiers, $src0,
137 (v2f16 (mixhi_inst $src0_modifiers, $src0,
150 (v2f16 (mixhi_inst $src0_modifiers, $src0,
246 (ops node:$src0, node:$src1),
273 (ops node:$src0, node:$src1),
282 (AMDGPUmul_u24_oneuse (and i32:$src0, (i32 65535)),
285 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> {
292 (AMDGPUmul_i24_oneuse (sext_inreg i32:$src0, i16),
[all …]
H A DSIInstrInfo.td620 (ops node:$src1, node:$src0),
621 (srl $src0, $src1)
625 (ops node:$src1, node:$src0),
626 (sra $src0, $src1)
631 (shl $src0, $src1)
636 (add (ctpop $src0), $src1)
641 (not (xor $src0, $src1))
1627 (ins Src0RC:$src0))
1839 string src0 = ", $src0";
1870 string src0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
[all …]
H A DVOP1Instructions.td15 bits<9> src0;
17 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, ?);
144 let Asm64 = "$vdst, $src0$clamp$omod";
179 (ins VRegOrLds_32:$src0),
180 "v_readfirstlane_b32 $vdst, $src0",
198 bits<9> src0;
200 let Inst{8-0} = src0;
306 // Restrict src0 to be VGPR
321 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
449 let Asm32 = " $vdst, $src0";
[all …]
H A DSIPeepholeSDWA.cpp308 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
343 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
537 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
577 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
645 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
661 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
721 OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
900 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::src0)) in pseudoOpConvertToVOP2()
909 .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::src0)) in pseudoOpConvertToVOP2()
1018 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
[all …]
H A DCaymanInstructions.td23 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU
26 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
63 (AMDGPUurecip i32:$src0),
64 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
H A DVOPCInstructions.td14 bits<9> src0;
17 let Inst{8-0} = src0;
52 let Asm32 = "$src0, $src1";
66 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
70 "$src0, $src1");
149 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
158 (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
769 (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
770 (i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64))
775 (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
[all …]
/freebsd-13.1/sys/libkern/
H A Dbcopy.c72 memcpy(void *dst0, const void *src0, size_t length) in memcpy() argument
79 src = src0; in memcpy()
152 (bcopy)(const void *src0, void *dst0, size_t length)
155 memcpy(dst0, src0, length);
/freebsd-13.1/lib/libc/string/
H A Dbcopy.c62 (void *dst0, const void *src0, size_t length) in memcpy() argument
67 bcopy(const void *src0, void *dst0, size_t length) in memcpy()
71 const char *src = src0; in memcpy()
/freebsd-13.1/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl3058 my ($a,$b,$src0) = @_;
3061 " mov $b, $src0
3071 my ($a,$src0) = @_;
3074 " mov 8*0+$a, $src0
3225 $src0 = "%rax";
3243 $src0 = "%rdx";
3421 mov $M(%rsp), $src0
3476 $src0 = "%rax";
3494 $src0 = "%rdx";
3856 $src0 = "%rax";
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td555 [(set target_regclass:$dst, (IntOP src_regclass:$src0))]>;
562 (ins s0_regclass:$src0, s1_regclass:$src1),
618 def INT_NVVM_MUL_RN_F : F_MATH_2<"mul.rn.f32 \t$dst, $src0, $src1;",
622 def INT_NVVM_MUL_RZ_F : F_MATH_2<"mul.rz.f32 \t$dst, $src0, $src1;",
626 def INT_NVVM_MUL_RM_F : F_MATH_2<"mul.rm.f32 \t$dst, $src0, $src1;",
827 def INT_NVVM_RCP_RN_F : F_MATH_1<"rcp.rn.f32 \t$dst, $src0;",
831 def INT_NVVM_RCP_RZ_F : F_MATH_1<"rcp.rz.f32 \t$dst, $src0;",
835 def INT_NVVM_RCP_RM_F : F_MATH_1<"rcp.rm.f32 \t$dst, $src0;",
839 def INT_NVVM_RCP_RP_F : F_MATH_1<"rcp.rp.f32 \t$dst, $src0;",
1055 "mov.b64 \t{$dst, %temp}, $src0;\n\t",
[all …]
/freebsd-13.1/sys/netipsec/
H A Dkey.c1942 struct sadb_address *src0, *dst0; in key_spdadd() local
2016 src0 + 1, in key_spdadd()
2163 struct sadb_address *src0, *dst0; in key_spddelete() local
2216 src0 + 1, in key_spddelete()
4816 struct sadb_address *src0, *dst0; in key_getspi() local
5300 struct sadb_address *src0, *dst0; in key_update() local
5526 struct sadb_address *src0, *dst0; in key_add() local
5956 struct sadb_address *src0, *dst0; in key_delete() local
6175 struct sadb_address *src0, *dst0; in key_get() local
6942 struct sadb_address *src0, *dst0; in key_acquire2() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAVX512.td1194 let Constraints = "$src0 = $dst" in
1235 let Constraints = "$src0 = $dst",
1494 VR512:$src0),
1502 VR512:$src0),
1511 VR512:$src0),
1519 VR512:$src0),
3983 def : Pat<(_.VT (OpNode _.RC:$src0,
3994 def : Pat<(_.VT (OpNode _.RC:$src0,
5134 _.RC:$src0)),
5148 _.RC:$src0)),
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DGenericOpcodes.td608 let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
615 let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
625 let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
632 let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
643 let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
726 let InOperandList = (ins type0:$src0, type1:$src1);
862 let InOperandList = (ins type0:$src0, type1:$src1);
1149 let InOperandList = (ins type1:$src0, variable_ops);
1158 let InOperandList = (ins type1:$src0, variable_ops);
1166 let InOperandList = (ins type1:$src0, variable_ops);
[all …]

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