Lines Matching refs:src0

188 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
191 // out = (src1 > src0) ? 1 : 0
227 //  Special case divide FMA with scale and flags (src0 = Quotient,
233 // Special case divide fixup and flags(src0 = Quotient, src1 =
252 // src0: vec4(src, 0, 0, mask)
321                       // i32 or f32 src0
386 def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
387   [(int_amdgcn_ldexp node:$src0, node:$src1),
388    (AMDGPUldexp_impl node:$src0, node:$src1)]>;
390 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
391   [(int_amdgcn_class node:$src0, node:$src1),
392   (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
394 def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
395   [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
396    (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
398 def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
399   [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
400    (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
414 def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
415   [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
416   (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
418 def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
419   [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
420   (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
422 def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
423   [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
424   (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
426 def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
427   [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
428   (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
430 def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
431   [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
432   (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
434 def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
435   [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
436    (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
438 def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
439   [(int_amdgcn_mul_u24 node:$src0, node:$src1),
440    (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
442 def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
443   [(int_amdgcn_mul_i24 node:$src0, node:$src1),
444    (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
446 def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
447   [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
448    (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
450 def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
451   [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
452    (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
454 def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
455   [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
456    (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
458 def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
459   [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
460    (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
462 def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
463   [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
464    (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
466 def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),
467   [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
468    (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;