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Searched refs:setRegClass (Results 1 – 25 of 26) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
142 setRegClass(Reg, NewRC); in recomputeRegClass()
H A DTailDuplicator.cpp427 MRI->setRegClass(VI->second.Reg, ConstrRC); in duplicateInstruction()
H A DMachineLICM.cpp1348 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
H A DRegisterCoalescer.cpp1444 MRI->setRegClass(DstReg, NewRC); in reMaterializeTrivialDef()
2083 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); in joinCopy()
H A DModuloSchedule.cpp1902 MRI.setRegClass(R, MRI.getRegClass(PhiR)); in rewriteUsesOf()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp199 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
251 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
825 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
H A DSILowerI1Copies.cpp565 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
691 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
H A DSIFoldOperands.cpp1708 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
1710 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
1716 MRI->setRegClass(Reg, TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg))); in tryFoldLoad()
H A DAMDGPUInstructionSelector.cpp167 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
441 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass); in selectG_UADDO_USUBO_UADDE_USUBE()
945 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1255 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectEndCfIntrinsic()
1824 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
2463 MRI->setRegClass( in selectG_AMDGPU_ATOMIC_CMPXCHG()
2502 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
H A DAMDGPURegisterBankInfo.cpp919 MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass); in executeInWaterfallLoop()
920 MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
921 MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
938 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass); in executeInWaterfallLoop()
951 MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass); in executeInWaterfallLoop()
952 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
H A DAMDGPULegalizerInfo.cpp2343 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
4880 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
4881 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
4916 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp178 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
H A DRegisterBankInfo.cpp146 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
H A DIRTranslator.cpp1633 MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF)); in getStackGuard()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp412 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1313 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1317 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1330 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1339 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2429 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2431 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
H A DPPCMIPeephole.cpp947 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
H A DPPCInstrInfo.cpp5054 MRI.setRegClass(RegToModify, NewRC); in transformToImmFormFedByLI()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp914 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
936 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
H A DAArch64InstructionSelector.cpp1977 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass); in preISelLower()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1310 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass); in foldMemoryOperandImpl()
1312 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass); in foldMemoryOperandImpl()
1314 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass); in foldMemoryOperandImpl()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp507 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h673 void setRegClass(Register Reg, const TargetRegisterClass *RC);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp648 MRI.setRegClass(Reg, Info.D.RC); in setupRegisterInfo()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp657 MRI->setRegClass(NewVReg, SRC); in EmitRegSequence()

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