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Searched refs:is64BitVector (Results 1 – 9 of 9) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h181 bool is64BitVector() const { in is64BitVector() function
182 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1933 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2118 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
2148 if (!is64BitVector) in SelectVLD()
2263 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
2302 } else if (is64BitVector) { in SelectVST()
2419 bool is64BitVector = VT.is64BitVector(); in SelectVLDSTLane() local
2457 if (!is64BitVector) in SelectVLDSTLane()
2483 if (is64BitVector) in SelectVLDSTLane()
2492 if (is64BitVector) in SelectVLDSTLane()
2955 bool is64BitVector = VT.is64BitVector(); in SelectVLDDup() local
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H A DARMISelLowering.cpp6385 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
7236 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
7272 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
7310 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
7343 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
9312 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
9313 Op1.getValueType().is64BitVector() && in LowerMUL()
12198 if (!N->getValueType(0).is64BitVector()) in AddCombineToVPADD()
12237 if (!N00.getValueType().is64BitVector() || in AddCombineVUZPToVPADDL()
13518 if (VT.is64BitVector() || VT.is128BitVector()) in PerformMULCombine()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp139 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
H A DAArch64ISelLowering.cpp3806 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
3807 Op1.getValueType().is64BitVector() && in LowerMUL()
5163 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
7122 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
8663 if (!SrcVT.is64BitVector()) { in ReconstructShuffle()
10612 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
13027 if (!VT.is64BitVector() && !VT.is128BitVector()) in tryCombineToBSL()
13253 if (!(VT.is64BitVector() || VT.is128BitVector())) in performANDCombine()
13666 if (!NarrowTy.is64BitVector()) in tryExtendDUPToExtractHigh()
13965 assert(LHS.getValueType().is64BitVector() && in tryCombineLongOpWithDup()
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H A DAArch64FastISel.cpp2925 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2969 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
H A DAArch64ISelDAGToDAG.cpp1364 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h398 bool is64BitVector() const { in is64BitVector() function
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp44040 N0.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()
44045 N1.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()