346                         bool is64BitVector);
1931                                        unsigned NumVecs, bool is64BitVector) {  in GetVLDSTAlign()  argument
1933   if (!is64BitVector && NumVecs < 3)  in GetVLDSTAlign()
2118   bool is64BitVector = VT.is64BitVector();  in SelectVLD()  local
2119   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVLD()
2148     if (!is64BitVector)  in SelectVLD()
2164   if (is64BitVector || NumVecs <= 2) {  in SelectVLD()
2165     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLD()
2233   unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);  in SelectVLD()
2263   bool is64BitVector = VT.is64BitVector();  in SelectVST()  local
2264   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVST()
2298   if (is64BitVector || NumVecs <= 2) {  in SelectVST()
2302     } else if (is64BitVector) {  in SelectVST()
2324     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVST()
2419   bool is64BitVector = VT.is64BitVector();  in SelectVLDSTLane()  local
2457     if (!is64BitVector)  in SelectVLDSTLane()
2483     if (is64BitVector)  in SelectVLDSTLane()
2492     if (is64BitVector)  in SelectVLDSTLane()
2503   unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLDSTLane()
2517   unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;  in SelectVLDSTLane()
2955   bool is64BitVector = VT.is64BitVector();  in SelectVLDDup()  local
2993   if (!is64BitVector)  in SelectVLDDup()
3009   unsigned Opc = is64BitVector    ? DOpcodes[OpcodeIndex]  in SelectVLDDup()
3025   if (is64BitVector || NumVecs == 1) {  in SelectVLDDup()
3058     unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;  in SelectVLDDup()