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Searched refs:getRegClassFor (Results 1 – 25 of 35) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp99 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
333 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
334 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
344 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
345 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
482 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
493 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
H A DInstrEmitter.cpp111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
217 const TargetRegisterClass *VTRC = TLI->getRegClassFor( in CreateVirtualRegisters()
280 const TargetRegisterClass *RC = TLI->getRegClassFor( in getVR()
390 ? TLI->getRegClassFor(OpVT, in AddOperand()
463 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
498 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
569 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
H A DFastISel.cpp324 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
804 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
1432 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1433 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
1465 const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty); in selectFreeze()
2119 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
H A DFunctionLoweringInfo.cpp376 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent)); in CreateReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg()
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt()
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock()
241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs()
H A DCallingConvLower.cpp258 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
H A DMachineScheduler.cpp2946 TLI->getRegClassFor(LegalIntVT)); in initPolicy()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp395 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
405 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
431 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
443 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
503 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
608 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
659 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
965 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
977 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
1559 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
[all …]
H A DARMISelLowering.h580 getRegClassFor(MVT VT, bool isDivergent = false) const override;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp472 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in X86FastEmitLoad()
2043 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
2203 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
2344 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2371 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2441 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); in X86SelectIntToFP()
2831 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerIntrinsicCall()
2913 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3119 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerArguments()
3718 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in X86MaterializeInt()
[all …]
H A DX86ISelDAGToDAG.cpp4479 unsigned RegClass = TLI->getRegClassFor(MaskVT)->getID(); in tryVPTESTM()
4517 unsigned RegClass = TLI->getRegClassFor(ResVT)->getID(); in tryVPTESTM()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1630 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1649 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1652 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicBinaryPartword()
1897 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1900 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicCmpSwapPartword()
2523 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
3673 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
4090 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
4102 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); in parseRegForInlineAsmConstraint()
4372 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
[all …]
H A DMipsSEISelDAGToDAG.cpp1265 TLI->getRegClassFor(ViaVecTy.getSimpleVT()); in trySelect()
1334 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); in trySelect()
H A DMipsFastISel.cpp1297 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp404 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
417 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
435 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
547 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg); in fastMaterializeFloatZero()
2874 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg); in selectIntToFP()
3107 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
3574 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3733 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h457 getRegClassFor(MVT VT, bool isDivergent) const override;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp516 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); in LowerCCCArguments()
1071 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp660 const TargetRegisterClass *RC = getRegClassFor(MVT::i64); in EmitSubregExt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp946 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
983 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT)); in LowerFormalArguments()
3210 auto *ARClass = getRegClassFor(SPTy); in LowerDYNAMIC_STACKALLOC()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1519 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); in finishCall()
1524 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp711 getRegClassFor(MVT::i16)); in LowerCCCArguments()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp848 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
1194 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp599 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
2684 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h851 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1227 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT)); in LowerFormalArguments()

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