Lines Matching refs:getRegClassFor

1630   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitSignExtendToI32InReg()
1649   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitAtomicBinaryPartword()
1652     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);  in emitAtomicBinaryPartword()
1845   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));  in emitAtomicCmpSwap()
1897   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitAtomicCmpSwapPartword()
1900     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);  in emitAtomicCmpSwapPartword()
2523   unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));  in lowerRETURNADDR()
3673       const TargetRegisterClass *RC = getRegClassFor(RegVT);  in LowerFormalArguments()
3752             getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));  in LowerFormalArguments()
4090     RC = getRegClassFor(VT);  in parseRegForInlineAsmConstraint()
4099     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);  in parseRegForInlineAsmConstraint()
4102     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);  in parseRegForInlineAsmConstraint()
4372   const TargetRegisterClass *RC = getRegClassFor(RegTy);  in copyByValRegs()
4491   const TargetRegisterClass *RC = getRegClassFor(RegTy);  in writeVarArgRegs()