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Searched refs:getRegClass (Results 1 – 25 of 202) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp460 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || in getAVOperandEncoding()
461 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || in getAVOperandEncoding()
462 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || in getAVOperandEncoding()
463 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || in getAVOperandEncoding()
464 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || in getAVOperandEncoding()
465 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || in getAVOperandEncoding()
466 MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) || in getAVOperandEncoding()
467 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || in getAVOperandEncoding()
468 MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg)) in getAVOperandEncoding()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 assert(RBGPR.covers(*TRI.getRegClass( in ARMRegisterBankInfo()
164 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
H A DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
271 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
516 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
517 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
533 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
539 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
640 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); in runOnInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
172 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
H A DWebAssemblyExplicitLocals.cpp275 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
308 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
380 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
411 typeForRegClass(MRI.getRegClass(Reg))); in runOnMachineFunction()
H A DWebAssemblyMemIntrinsicResults.cpp171 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg)) in optimizeCall()
H A DWebAssemblyRegColoring.cpp140 const TargetRegisterClass *RC = MRI->getRegClass(Old); in runOnMachineFunction()
145 if (MRI->getRegClass(SortedIntervals[C]->reg()) != RC) in runOnMachineFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp134 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
148 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
155 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
199 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
223 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
268 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence()
685 DstRC = MRI->getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
686 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
687 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
805 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg()); in processPHINode()
[all …]
H A DSIInstrInfo.cpp1056 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in insertVectorSelect()
2555 if (MRI.getRegClass(FalseReg) != RC) in canInsertSelect()
2570 if (MRI.getRegClass(FalseReg) != RC) in canInsertSelect()
4550 return RI.getRegClass(RegClass); in getRegClass()
4562 return MRI.getRegClass(Reg); in getOpRegClass()
4568 return RI.getRegClass(RCID); in getOpRegClass()
4966 if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) && in legalizeOperandsVOP3()
6406 MRI.getRegClass(Src0.getReg()) : in splitScalar64BitUnaryOp()
6536 MRI.getRegClass(Src0.getReg()) : in splitScalar64BitBinaryOp()
6541 MRI.getRegClass(Src1.getReg()) : in splitScalar64BitBinaryOp()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocBase.cpp106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); in allocatePhysRegs()
187 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); in enqueue()
H A DPeepholeOptimizer.cpp477 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
488 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
574 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
603 RC = MRI->getRegClass(UseMI->getOperand(0).getReg()); in INITIALIZE_PASS_DEPENDENCY()
689 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource()
751 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); in findNextSource()
781 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
1252 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1440 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg)) in foldRedundantCopy()
1975 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) || in getNextSourceFromInsertSubreg()
H A DDetectDeadLanes.cpp155 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy()
251 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
370 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes()
435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
484 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput()
H A DRegAllocFast.cpp330 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
425 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
479 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in reload()
748 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtReg()
843 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtRegUndef()
974 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in useVirtReg()
1078 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts()
1081 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in addRegClassDefCounts()
1092 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in addRegClassDefCounts()
1204 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in allocateInstruction()
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H A DMachineLoopUtils.cpp55 R = MRI.createVirtualRegister(MRI.getRegClass(OrigR)); in PeelSingleBlockLoop()
67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg())); in PeelSingleBlockLoop()
H A DModuloSchedule.cpp547 const TargetRegisterClass *RC = MRI.getRegClass(Def); in generateExistingPhis()
663 const TargetRegisterClass *RC = MRI.getRegClass(Def); in generatePhis()
1037 const TargetRegisterClass *RC = MRI.getRegClass(reg); in updateInstruction()
1188 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1432 LoopReg = phi(LoopReg, *DefaultI++, MRI.getRegClass(Reg)); in remapUse()
1440 auto RC = MRI.getRegClass(Reg); in remapUse()
1491 RC = MRI.getRegClass(LoopReg); in phi()
1494 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
1636 auto RC = MRI.getRegClass(PhiR); in moveStageBetweenBlocks()
1853 auto RC = MRI.getRegClass(MI.getOperand(0).getReg()); in CreateLCSSAExitingBlock()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp115 unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs(); in INITIALIZE_PASS_DEPENDENCY()
121 if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID) in INITIALIZE_PASS_DEPENDENCY()
174 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY()
H A DX86InstructionSelector.cpp129 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
198 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getRegClass() function in X86InstructionSelector
201 return getRegClass(Ty, RegBank); in getRegClass()
249 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
279 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
728 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
729 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
814 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI)); in selectZext()
857 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
858 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectAnyext()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
133 MRI.getRegClass(AddendSrcReg)) in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
238 MRI.getRegClass(OldFMAReg))) in processBlock()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp140 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
337 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
436 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
480 if (MRI->getRegClass(DR.R) != PredRC) in eliminatePredCopies()
482 if (MRI->getRegClass(SR.R) != PredRC) in eliminatePredCopies()
H A DHexagonSplitDouble.cpp228 if (MRI->getRegClass(R) == DoubleRC) in partitionRegisters()
266 if (MRI->getRegClass(T) != DoubleRC) in partitionRegisters()
502 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass); in collectIndRegsForLoop()
516 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC) in collectIndRegsForLoop()
518 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC) in collectIndRegsForLoop()
538 if (MRI->getRegClass(R) == DoubleRC) in collectIndRegsForLoop()
606 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) { in createHalfInstr()
672 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg()); in splitMemRef()
1003 if (MRI->getRegClass(DstR) == DoubleRC) { in splitInstr()
1107 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg()) in collapseRegPairs()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp139 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
164 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
211 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
240 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
321 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
449 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
516 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
573 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
614 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
631 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg()
38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()

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