992   const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);  in materializeImmediate()
1056     RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in insertVectorSelect()
1057   assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&  in insertVectorSelect()
2554     const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);  in canInsertSelect()
2555     if (MRI.getRegClass(FalseReg) != RC)  in canInsertSelect()
2569     const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);  in canInsertSelect()
2570     if (MRI.getRegClass(FalseReg) != RC)  in canInsertSelect()
2598   const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);  in insertSelect()
2841       if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))  in FoldImmediate()
2844       if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))  in FoldImmediate()
2911                      RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))  in FoldImmediate()
2927                     RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))  in FoldImmediate()
3679     return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));  in usesConstantBus()
3881       const TargetRegisterClass *RC = RI.getRegClass(RegClass);  in verifyInstruction()
4404       const TargetRegisterClass &RC = *MRI.getRegClass(Reg);  in verifyInstruction()
4521 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,  in getRegClass()  function in SIInstrInfo
4550   return RI.getRegClass(RegClass);  in getRegClass()
4562       return MRI.getRegClass(Reg);  in getOpRegClass()
4568   return RI.getRegClass(RCID);  in getOpRegClass()
4577   const TargetRegisterClass *RC = RI.getRegClass(RCID);  in legalizeOpWithMove()
4667   const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);  in isLegalRegOperand()
4671   const TargetRegisterClass *RC = MRI.getRegClass(Reg);  in isLegalRegOperand()
4704       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;  in isOperandLegal()
4920     if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {  in legalizeOperandsVOP3()
4926     if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {  in legalizeOperandsVOP3()
4966     if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) &&  in legalizeOperandsVOP3()
4972     if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))  in legalizeOperandsVOP3()
4993   const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);  in readlaneVGPRToSGPR()
5041   if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {  in legalizeOperandsSMRD()
5046   if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {  in legalizeOperandsSMRD()
5141   if (!SAddr || RI.isSGPRClass(MRI.getRegClass(SAddr->getReg())))  in legalizeOperandsFLAT()
5211   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in emitLoadSRsrcFromVGPRLoop()
5270   auto SRsrcRC = TRI->getEquivalentSGPRClass(MRI.getRegClass(VRsrc));  in emitLoadSRsrcFromVGPRLoop()
5325   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in loadSRsrcFromVGPR()
5470           MRI.getRegClass(MI.getOperand(i).getReg());  in legalizeOperands()
5531         const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());  in legalizeOperands()
5549     const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);  in legalizeOperands()
5550     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);  in legalizeOperands()
5562     if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))  in legalizeOperands()
5575     if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg())))  in legalizeOperands()
5579     if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg())))  in legalizeOperands()
5588     if (!RI.isSGPRClass(MRI.getRegClass(Dest->getReg()))) {  in legalizeOperands()
5619     if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),  in legalizeOperands()
5620                              RI.getRegClass(RsrcRC))) {  in legalizeOperands()
5649       const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in legalizeOperands()
5959       const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in moveToVALU()
5971           MRI.getRegClass(Inst.getOperand(0).getReg())));  in moveToVALU()
5999           RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg()));  in moveToVALU()
6297                       RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));  in lowerScalarXnor()
6299                       RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));  in lowerScalarXnor()
6406     MRI.getRegClass(Src0.getReg()) :  in splitScalar64BitUnaryOp()
6414   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());  in splitScalar64BitUnaryOp()
6456   const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in splitScalar64BitAddSub()
6471   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());  in splitScalar64BitAddSub()
6472   const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());  in splitScalar64BitAddSub()
6536     MRI.getRegClass(Src0.getReg()) :  in splitScalar64BitBinaryOp()
6541     MRI.getRegClass(Src1.getReg()) :  in splitScalar64BitBinaryOp()
6555   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());  in splitScalar64BitBinaryOp()
6598   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());  in splitScalar64BitXnor()
6640     MRI.getRegClass(Src.getReg()) :  in splitScalar64BitBCNT()
6991     const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);  in findUsedSGPR()
6998     const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);  in findUsedSGPR()
7446   return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);  in isBufferSMRD()
7870       const TargetRegisterClass *RC = MRI.getRegClass(VirtReg);  in foldMemoryOperandImpl()