Home
last modified time | relevance | path

Searched refs:getOperand (Results 1 – 25 of 962) sorted by relevance

12345678910>>...39

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp662 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
678 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
694 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
708 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
726 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
820 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
838 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
1268 if (MI->getOperand(2).isImm() && in EmitAnyX86InstComments()
1269 MI->getOperand(3).isImm()) in EmitAnyX86InstComments()
1278 if (MI->getOperand(3).isImm() && in EmitAnyX86InstComments()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
111 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
112 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
121 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
122 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
[all …]
H A DSystemZAsmPrinter.h39 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
40 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
43 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
44 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
45 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
46 return A.getOperand(1).getImm() < B.getOperand(1).getImm(); in operator()
47 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
48 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
49 if (A.getOperand(4).getImm() != B.getOperand(4).getImm()) in operator()
50 return A.getOperand(4).getImm() < B.getOperand(4).getImm(); in operator()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock()
246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
252 MI.getOperand(3).setSubReg(AddSubReg); in processBlock()
255 MI.getOperand(3).setIsKill(AddRegKill); in processBlock()
258 MI.getOperand(3).setIsUndef(AddRegUndef); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
266 MI.getOperand(2).setSubReg(AddSubReg); in processBlock()
267 MI.getOperand(2).setIsKill(AddRegKill); in processBlock()
[all …]
H A DPPCMIPeephole.cpp177 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
183 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
470 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != 0) in simplifyCode()
611 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
784 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
828 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
870 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) in simplifyCode()
1347 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { in eliminateRedundantCompare()
1497 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); in eliminateRedundantCompare()
1566 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); in emitRLDICWhenLoweringJumpTables()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp127 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
128 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
143 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
144 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
152 if (LatrCFAlu.getOperand(Mode0Idx).getImm()) { in mergeIfPossible()
153 RootCFAlu.getOperand(Mode0Idx).setImm( in mergeIfPossible()
155 RootCFAlu.getOperand(KBank0Idx).setImm( in mergeIfPossible()
157 RootCFAlu.getOperand(KBank0LineIdx) in mergeIfPossible()
161 RootCFAlu.getOperand(Mode1Idx).setImm( in mergeIfPossible()
163 RootCFAlu.getOperand(KBank1Idx).setImm( in mergeIfPossible()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp89 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
95 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
97 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
98 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
112 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
133 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX()
139 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
164 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandRRM()
170 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandRRM()
195 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandHM()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp180 MIBHI->getOperand(4).setIsKill(); in expandArith()
205 MIBLO->getOperand(3).setIsDead(); in expandLogic()
326 MIBHI->getOperand(4).setIsKill(); in expand()
358 MIBLO->getOperand(4).setIsKill(); in expand()
369 MIBHI->getOperand(4).setIsKill(); in expand()
1333 MIB->getOperand(2).setIsKill(); in expand()
1425 MI0->getOperand(3).setIsDead(); in expandLSLW4Rd()
1434 MI1->getOperand(3).setIsDead(); in expandLSLW4Rd()
1443 MI2->getOperand(3).setIsDead(); in expandLSLW4Rd()
1511 MI0->getOperand(3).setIsDead(); in expandLSLW12Rd()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp85 HiLUI.getOperand(1).getOffset() != 0 || in INITIALIZE_PASS()
93 LoADDI->getOperand(2).getOffset() != 0 || in INITIALIZE_PASS()
106 HiLUI.getOperand(1).setOffset(Offset); in foldOffset()
107 LoADDI.getOperand(2).setOffset(Offset); in foldOffset()
110 MRI->replaceRegWith(Tail.getOperand(0).getReg(), in foldOffset()
138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset()
139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset()
192 int64_t Offset = Tail.getOperand(2).getImm(); in detectAndFoldOffset()
233 if (Tail.getOperand(1).isFI()) in detectAndFoldOffset()
243 HiLUI.getOperand(1).setOffset(Offset); in detectAndFoldOffset()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp101 const MCOperand &Dst = MI->getOperand(0); in printInst()
102 const MCOperand &MO1 = MI->getOperand(1); in printInst()
103 const MCOperand &MO2 = MI->getOperand(2); in printInst()
104 const MCOperand &MO3 = MI->getOperand(3); in printInst()
124 const MCOperand &Dst = MI->getOperand(0); in printInst()
166 MI->getOperand(3).getImm() == -4) { in printInst()
195 MI->getOperand(4).getImm() == 4) { in printInst()
290 switch (MI->getOperand(0).getImm()) { in printInst()
997 if (MI->getOperand(OpNum).getReg()) { in printSBitModifierOperand()
1007 O << MI->getOperand(OpNum).getImm(); in printNoHashImmediate()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
177 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
178 N->getOperand(2), N->getOperand(3) }; in Select()
184 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
185 N->getOperand(2), N->getOperand(3) }; in Select()
191 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
192 N->getOperand(2), N->getOperand(3) }; in Select()
198 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; in Select()
241 SDValue Chain = N->getOperand(0); in tryBRIND()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp211 Rt = L.getOperand(0); in getCompoundInsn()
222 Rt = L.getOperand(0); in getCompoundInsn()
223 Rs = L.getOperand(1); in getCompoundInsn()
236 Rs = L.getOperand(1); in getCompoundInsn()
237 Rt = L.getOperand(2); in getCompoundInsn()
249 Rs = L.getOperand(1); in getCompoundInsn()
250 Rt = L.getOperand(2); in getCompoundInsn()
262 Rs = L.getOperand(1); in getCompoundInsn()
263 Rt = L.getOperand(2); in getCompoundInsn()
283 Rs = L.getOperand(1); in getCompoundInsn()
[all …]
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp41 int FrameIdx = MI->getOperand(1).getIndex(); in computeKnownAlignment()
54 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
255 int FrameIdx = MI.getOperand(1).getIndex(); in computeKnownBitsImpl()
324 computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(), in computeKnownBitsImpl()
449 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
455 SrcBitWidth = MI.getOperand(2).getImm(); in computeKnownBitsImpl()
502 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
589 MachineOperand &Src = MI.getOperand(1); in computeNumSignBits()
599 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
607 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
[all …]
H A DCombinerHelper.cpp683 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
996 matchEqualDefs(MI.getOperand(2), UseMI.getOperand(2))) { in matchCombineDivRem()
1032 {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()}); in applyCombineDivRem()
2765 return matchEqualDefs(MI.getOperand(2), MI.getOperand(3)) && in matchSelectSameVal()
2766 canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(2).getReg(), in matchSelectSameVal()
2771 return matchEqualDefs(MI.getOperand(1), MI.getOperand(2)) && in matchBinOpSameVal()
2772 canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), in matchBinOpSameVal()
3299 replaceRegWith(MRI, MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applyNotCmp()
3343 MI.getOperand(1).setReg(Not->getOperand(0).getReg()); in applyXorOfAndWithSameReg()
3369 Builder.buildIntToPtr(MI.getOperand(0), MI.getOperand(2)); in applyPtrAddZero()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp62 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
70 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
116 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
117 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
758 assert(MI.getOperand(OpNo).isReg()); in getMemEncoding()
774 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4()
788 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl1()
802 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl2()
846 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm9()
860 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm11()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp148 .add(MI.getOperand(0)) in expandMOVImm()
498 MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
507 (MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg() && in expand_DestructiveOp()
508 MI.getOperand(DOPIdx).getReg() != MI.getOperand(Src2Idx).getReg()); in expand_DestructiveOp()
1087 .add(MI.getOperand(0)) in expandMI()
1088 .add(MI.getOperand(1)) in expandMI()
1089 .add(MI.getOperand(2)) in expandMI()
1159 .add(MI.getOperand(0)) in expandMI()
1160 .add(MI.getOperand(1)); in expandMI()
1188 .add(MI.getOperand(0)) in expandMI()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp190 MIB.add(MI->getOperand(0)); in RevertWhileLoopSetup()
191 MIB.add(MI->getOperand(1)); in RevertWhileLoopSetup()
249 .add(WLSIt->getOperand(1)); in LowerWhileLoopStart()
452 VCTP->getOperand(0).getReg() != FirstVCTP->getOperand(0).getReg()) { in ConvertTailPredLoop()
558 MachineOperand &CondOP1 = Cond.getOperand(1), &CondOP2 = Cond.getOperand(2); in IsVPNOTEquivalent()
559 MachineOperand &PrevOP1 = Prev.getOperand(1), &PrevOP2 = Prev.getOperand(2); in IsVPNOTEquivalent()
989 .add(MI.getOperand(0)) in ConvertVPSEL()
990 .add(MI.getOperand(1)) in ConvertVPSEL()
991 .add(MI.getOperand(1)) in ConvertVPSEL()
993 .add(MI.getOperand(4)) in ConvertVPSEL()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp2378 N0.getOperand(0) == N1.getOperand(1)) in visitADDLike()
2384 N0.getOperand(1) == N1.getOperand(0)) in visitADDLike()
2390 N0 == N1.getOperand(1).getOperand(0)) in visitADDLike()
2396 N0 == N1.getOperand(1).getOperand(1)) in visitADDLike()
2403 N0 == N1.getOperand(0).getOperand(1)) in visitADDLike()
3401 N0.getOperand(1).getOperand(0) == N1) in visitSUB()
3407 N0.getOperand(1).getOperand(1) == N1) in visitSUB()
3413 N0.getOperand(1).getOperand(1) == N1) in visitSUB()
8675 N0.getOperand(0).getOperand(1) == N1 && N0.getOperand(0).hasOneUse()) { in visitSRA()
14209 U->getOperand(0) == U->getOperand(1).getOperand(0) && in combineRepeatedFPDivisors()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1017 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3)); in expandPostRAPseudo()
2655 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2656 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3854 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3975 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
4014 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4023 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4128 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) in getDuplexCandidateGroup()
4138 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4163 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) || in getDuplexCandidateGroup()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
152 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
165 const MCOperand &Op = MI->getOperand(OpNo); in printMemImmOperand()
179 const MCOperand &Op = MI->getOperand(OpNo); in printHi16ImmOperand()
191 const MCOperand &Op = MI->getOperand(OpNo); in printHi16AndImmOperand()
203 const MCOperand &Op = MI->getOperand(OpNo); in printLo16AndImmOperand()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp262 .add(I.getOperand(0)) in buildUnalignedStore()
343 .add(I.getOperand(0)) in select()
344 .add(I.getOperand(1)) in select()
355 .add(I.getOperand(0)) in select()
356 .add(I.getOperand(1)) in select()
362 .add(I.getOperand(0)) in select()
502 .add(I.getOperand(0)) in select()
538 .add(I.getOperand(0)) in select()
539 .add(I.getOperand(2)) in select()
540 .add(I.getOperand(1)) in select()
[all …]
H A DMipsSEISelLowering.cpp978 N->getOperand(1), N->getOperand(2)); in performSETCCCombine()
992 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
1620 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1635 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1639 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1680 Op->getOperand(1), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1903 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1913 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1963 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1981 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
[all …]
H A DMicroMipsSizeReduction.cpp310 if (!MI->getOperand(Op).isImm()) in GetImm()
371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg())) in CheckXWPInstr()
448 if (!IsSP(MI->getOperand(1))) in ReduceXWtoXWSP()
517 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1))) in ReduceADDIUToADDIUR1SP()
535 if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1))) in ReduceADDIUToADDIUSP()
664 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) && in ReduceXORtoXOR16()
665 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg())) in ReduceXORtoXOR16()
714 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
717 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
718 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineNegator.cpp124 std::array<Value *, 2> Ops{I->getOperand(0), I->getOperand(1)}; in getSortedOperandsOfBinOp()
194 ? Builder.CreateLShr(I->getOperand(0), I->getOperand(1)) in visitImpl()
195 : Builder.CreateAShr(I->getOperand(0), I->getOperand(1)); in visitImpl()
227 return Builder.CreateSub(I->getOperand(1), I->getOperand(0), in visitImpl()
266 Value *NegOp = negate(I->getOperand(0), Depth + 1); in visitImpl()
288 if (isKnownNegation(I->getOperand(1), I->getOperand(2))) { in visitImpl()
300 Value *NegOp1 = negate(I->getOperand(1), Depth + 1); in visitImpl()
346 Value *NegOp = negate(I->getOperand(0), Depth + 1); in visitImpl()
356 auto *Op1C = dyn_cast<Constant>(I->getOperand(1)); in visitImpl()
360 I->getOperand(0), in visitImpl()
[all …]

12345678910>>...39