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Searched refs:getNode (Results 1 – 25 of 191) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1258 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); in SExtPromoteOperand()
1273 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); in ZExtPromoteOperand()
4603 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && in SimplifyNodeWithTwoResults()
7027 if (LHSMask.getNode() || RHSMask.getNode()) { in MatchRotate()
7050 if (LHSMask.getNode() || RHSMask.getNode()) in MatchRotate()
11057 if (NarrowLoad.getNode() != N0.getNode()) { in visitSIGN_EXTEND()
11209 if (NewXor.getNode() == N0.getNode()) { in visitSIGN_EXTEND()
11321 if (NarrowLoad.getNode() != N0.getNode()) { in visitZERO_EXTEND()
11564 if (NarrowLoad.getNode() != N0.getNode()) { in visitANY_EXTEND()
15167 if (Tmp.getNode() == N.getNode()) in rebuildSetCC()
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H A DLegalizeIntegerTypes.cpp239 if (Res.getNode()) in PromoteIntegerResult()
478 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
536 return DAG.getNode( in PromoteIntRes_CTLZ()
1572 if (Res.getNode() == N) in PromoteIntegerOperand()
2257 if (Lo.getNode()) in ExpandIntegerResult()
3032 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), in ExpandIntRes_CTPOP()
3300 Lo = DAG.getNode( in ExpandIntRes_LOAD()
3884 Hi = DAG.getNode( in ExpandIntRes_SIGN_EXTEND()
4357 if (!LoCmp.getNode()) in IntegerExpandSetCCOperands()
4364 if (!HiCmp.getNode()) in IntegerExpandSetCCOperands()
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H A DResourcePriorityQueue.cpp78 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
116 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
244 if (!SU || !SU->getNode()) in isResourceAvailable()
249 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
254 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
294 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
298 SU->getNode()->getMachineOpcode())); in reserveResources()
326 if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode()) in rawRegPressureDelta()
341 if (isa<ConstantSDNode>(Op.getNode())) in rawRegPressureDelta()
360 if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode()) in regPressureDelta()
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H A DLegalizeDAG.cpp587 Hi = DAG.getNode( in LegalizeStoreOps()
598 Hi = DAG.getNode( in LegalizeStoreOps()
810 Hi = DAG.getNode( in LegalizeLoadOps()
838 Hi = DAG.getNode( in LegalizeLoadOps()
1366 if (!Ch.getNode()) { in ExpandExtractFromVectorThroughStack()
1893 if (!Value1.getNode()) in ExpandBUILD_VECTOR()
3466 Tmp2 = DAG.getNode( in ExpandNode()
3575 if (Tmp3.getNode()) in ExpandNode()
3678 if (CC.getNode()) { in ExpandNode()
4421 Tmp1 = DAG.getNode( in PromoteNode()
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H A DTargetLowering.cpp503 return TLO.New.getNode(); in ShrinkDemandedConstant()
580 SDValue X = DAG.getNode( in ShrinkDemandedOp()
6307 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || in expandMUL_LOHI()
6308 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())); in expandMUL_LOHI()
6328 if (!LL.getNode() && !RL.getNode() && in expandMUL_LOHI()
6334 if (!LL.getNode()) in expandMUL_LOHI()
6375 if (!LH.getNode() && !RH.getNode() && in expandMUL_LOHI()
6384 if (!LH.getNode()) in expandMUL_LOHI()
6626 DAG.getNode(HsOpc, DL, VT, DAG.getNode(HsOpc, DL, VT, Op0, One), HsAmt); in expandROT()
7012 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33), in expandCTPOP()
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H A DLegalizeVectorTypes.cpp192 if (R.getNode()) in ScalarizeVectorResult()
545 Src = DAG.getNode( in ScalarizeVecRes_FP_TO_XINT_SAT()
676 if (Res.getNode() == N) in ScalarizeVectorOperand()
1088 if (Lo.getNode()) in SplitVectorResult()
1266 Hi = DAG.getNode( in SplitVecRes_EXTRACT_SUBVECTOR()
1545 SDNode *LoNode = DAG.getNode(Opcode, dl, LoVTs, LoLHS, LoRHS).getNode(); in SplitVecRes_OverflowOp()
1546 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode(); in SplitVecRes_OverflowOp()
2243 if (Res.getNode() == N) in SplitVectorOperand()
3165 if (Res.getNode()) in WidenVectorResult()
4604 if (Res.getNode() == N) in WidenVectorOperand()
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H A DLegalizeTypesGeneric.cpp58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
139 Vals.push_back(DAG.getNode( in ExpandRes_BITCAST()
230 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, in ExpandRes_EXTRACT_VECTOR_ELT()
425 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, in ExpandOp_INSERT_VECTOR_ELT()
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H A DSelectionDAGBuilder.cpp289 return DAG.getNode( in getCopyFromParts()
1215 if (Val.getNode()) { in resolveDanglingDebugInfo()
1349 if (N.getNode()) { in handleDebugValue()
1476 if (N.getNode()) return N; in getValue()
1495 if (N.getNode()) { in getNonRegisterValue()
4891 SDValue t1 = DAG.getNode( in GetExponent()
5608 if (!Op && N.getNode()) { in EmitFuncArgumentDbgValue()
5626 if (!Op && N.getNode()) { in EmitFuncArgumentDbgValue()
6075 if (N.getNode()) { in visitIntrinsicCall()
7434 assert((Result.second.getNode() || !Result.first.getNode()) && in lowerInvokable()
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H A DLegalizeVectorOps.cpp547 if (!Res.getNode()) in LowerOperationWrapper()
631 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
1024 return DAG.getNode( in ExpandANY_EXTEND_VECTOR_INREG()
1045 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
1088 return DAG.getNode(ISD::BITCAST, DL, VT, in ExpandZERO_EXTEND_VECTOR_INREG()
1114 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBSWAP()
1148 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBITREVERSE()
1207 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); in ExpandVSELECT()
1208 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
1378 if (CC.getNode()) in ExpandSETCC()
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H A DLegalizeFloatTypes.cpp153 if (R.getNode()) { in SoftenFloatResult()
854 if (Res.getNode() == N) in SoftenFloatOperand()
912 if (!NewRHS.getNode()) { in SoftenFloatOp_BR_CC()
1023 if (NewRHS.getNode()) { in SoftenFloatOp_SETCC()
1259 if (Lo.getNode()) in ExpandFloatResult()
1797 if (Res.getNode() == N) in ExpandFloatOperand()
2098 if (R.getNode()) in PromoteFloatOperand()
2289 if (R.getNode()) in PromoteFloatResult()
2508 return DAG.getNode( in PromoteFloatRes_XINT_TO_FP()
2652 if (R.getNode()) in SoftPromoteHalfResult()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1567 SDValue Hi = DAG.getNode( in splitVector()
1621 Join = DAG.getNode( in SplitVectorLoad()
2065 Z = DAG.getNode(ISD::ADD, DL, VT, Z, in LowerUDIVREM()
2071 DAG.getNode(ISD::SUB, DL, VT, X, DAG.getNode(ISD::MUL, DL, VT, Q, Y)); in LowerUDIVREM()
3139 DCI.AddToWorklist(Lo.getNode()); in splitBinaryBitConstantOpImpl()
3140 DCI.AddToWorklist(Hi.getNode()); in splitBinaryBitConstantOpImpl()
3267 return DAG.getNode( in performSrlCombine()
3486 DCI.AddToWorklist(Mulhi.getNode()); in performMulhsCombine()
3519 DCI.AddToWorklist(Mulhi.getNode()); in performMulhuCombine()
3602 DCI.AddToWorklist(NewSelect.getNode()); in distributeOpThroughSelect()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/BinaryFormat/
H A DMsgPackDocument.cpp80 *this = getDocument()->getNode(Val); in operator =()
84 *this = getDocument()->getNode(Val); in operator =()
88 *this = getDocument()->getNode(Val); in operator =()
92 *this = getDocument()->getNode(Val); in operator =()
96 *this = getDocument()->getNode(Val); in operator =()
153 Node = getNode(); in readFromBlob()
156 Node = getNode(Obj.Int); in readFromBlob()
159 Node = getNode(Obj.UInt); in readFromBlob()
162 Node = getNode(Obj.Bool); in readFromBlob()
165 Node = getNode(Obj.Float); in readFromBlob()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp434 return DAG.getNode(ISD::SHL, dl, MVT::i32, in convertToByteIndex()
518 if (!SplatV.getNode()) in buildHvxVectorReg()
526 assert(SplatV.getNode()); in buildHvxVectorReg()
569 if (Vec.getNode() != nullptr && T.getNode() != Vec.getNode()) in buildHvxVectorReg()
1264 for (SDValue V : Op.getNode()->ops()) in LowerHvxConcatVectors()
1314 ArrayRef<SDUse> U(Op.getNode()->ops()); in LowerHvxConcatVectors()
1468 SDValue A = DAG.getNode(ISD::AND, dl, ResTy, in LowerHvxCttz()
1471 return DAG.getNode(ISD::SUB, dl, ResTy, in LowerHvxCttz()
1628 SDValue C = DAG.getNode( in LowerHvxBitcast()
1781 for (SDValue A : Op.getNode()->ops()) { in SplitHvxPairOp()
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H A DHexagonISelDAGToDAG.cpp272 SDNode *C = Ch.getNode(); in tryLoadOfLoadIntrinsic()
300 if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(3).getNode()) in tryLoadOfLoadIntrinsic()
1079 ReplaceNode(T0.getNode(), NewShl.getNode()); in ppAddrReorderAddShl()
1155 ReplaceNode(T0.getNode(), NewShl.getNode()); in ppAddrRewriteAndSrl()
1663 assert(A.Value.getNode() && B.Value.getNode()); in Compare()
1909 if ((!isOpcodeHandled(Op0.getNode()) || RootWeights.count(Op0.getNode())) && in balanceSubTree()
1910 (!isOpcodeHandled(Op1.getNode()) || RootWeights.count(Op1.getNode()))) { in balanceSubTree()
1974 if (Child.getNode() != N && RootWeights.count(Child.getNode())) { in balanceSubTree()
2139 if (GA.Value.getNode()) in balanceSubTree()
2170 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || in balanceSubTree()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3223 if (Flag.getNode()) in LowerReturn()
5058 if (True.getNode() && False.getNode()) { in LowerSELECT()
12193 if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() || in AddCombineToVPADD()
12231 if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() || in AddCombineVUZPToVPADDL()
12494 if (AddcSubcOp0.getNode() == AddcSubcOp1.getNode()) in AddCombineTo64bitMLAL()
12515 if (AddeSubeOp0.getNode() == AddeSubeOp1.getNode()) in AddCombineTo64bitMLAL()
13763 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) || in PerformORCombineToSMULWBT()
14367 Op0.getNode() == Op1.getNode() && in PerformVMOVDRRCombine()
14767 DCI.CombineTo(OtherExt.getNode(), SDValue(VMOVRRD.getNode(), 1)); in PerformExtractEltToVMOVRRD()
17108 DAG.ReplaceAllUsesWith(Int.getNode(), LoopDec.getNode()); in PerformHWLoopCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp41 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
44 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
104 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
119 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
136 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
145 SDValue LenMinus1 = DAG.getNode(ISD::ADD, DL, MVT::i64, in EmitTargetCodeForMemset()
185 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, in addIPMSequence()
187 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence()
215 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char, in EmitTargetCodeForMemchr()
229 End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, PtrVT, Ops); in EmitTargetCodeForMemchr()
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H A DSystemZISelDAGToDAG.cpp78 if (Base.getNode()) in dump()
79 Base.getNode()->dump(DAG); in dump()
85 if (Index.getNode()) in dump()
596 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode())) in selectAddress()
634 if (!Base.getNode()) in getAddressOperands()
662 if (!Index.getNode()) in getAddressOperands()
707 Regs[0].getNode() && Regs[1].getNode()) { in selectBDVAddr12Only()
1017 N = New.getNode(); in tryRISBGZero()
1121 if (Op0.getNode()) in splitLargeImmediate()
1147 SelectCode(Or.getNode()); in splitLargeImmediate()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp550 SDValue Lo(Hi.getNode(), 1); in LowerSMUL_LOHI()
567 SDValue Lo(Hi.getNode(), 1); in LowerUMUL_LOHI()
664 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
672 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
683 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
724 SDValue Carry(Lo.getNode(), 1); in ExpandADDSUB()
728 SDValue Ignored(Hi.getNode(), 1); in ExpandADDSUB()
738 SDNode *Node = Op.getNode(); in LowerVAARG()
1215 if (InFlag.getNode()) in LowerCCCCallTo()
1512 if (Flag.getNode()) in LowerReturn()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3322 return DAG.getNode( in LowerVectorFP_TO_INT()
3362 return DAG.getNode( in LowerFP_TO_INT()
3475 return DAG.getNode( in LowerINT_TO_FP()
4041 return DAG.getNode( in LowerINTRINSIC_WO_CHAIN()
4047 return DAG.getNode( in LowerINTRINSIC_WO_CHAIN()
4053 return DAG.getNode( in LowerINTRINSIC_WO_CHAIN()
6352 if (Flag.getNode()) in LowerReturn()
6409 return DAG.getNode( in getAddrLarge()
7127 Val = DAG.getNode( in LowerCTPOP()
10917 if (!Cmp.getNode()) in LowerVSETCC()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp354 if (Result.getNode()) { in LowerAsmOperandForConstraint()
586 if (Flag.getNode()) in LowerReturn()
590 return DAG.getNode(Opc, DL, MVT::Other, in LowerReturn()
690 if (StackPtr.getNode() == nullptr) in LowerCCCCallTo()
751 if (InFlag.getNode()) in LowerCCCCallTo()
946 Res = DAG.getNode(ISD::SHL, DL, VT, V, in LowerMUL()
1140 return DAG.getNode(ISD::OR, DL, MVT::i32, in LowerConstantPool()
1305 SDValue NegatedPlus32 = DAG.getNode( in LowerSRL_PARTS()
1447 if (N0.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1450 if (N1.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2876 if (Flag.getNode()) in LowerReturn()
4413 if (InFlag.getNode()) in LowerCall()
8345 if (!V1.getNode()) in LowerBuildVectorv4x32()
10429 assert(!VarElt.getNode() && !InsIndex.getNode() && in LowerBUILD_VECTOR()
10533 if (Op.getNode()->isOnlyUserOf(Item.getNode())) in LowerBUILD_VECTOR()
21890 Res = DAG.getNode( in LowerFP_TO_FP16()
22804 if (!Src.getNode()) in LowerAndToBT()
29040 M = DAG.getNode( in LowerRotate()
29050 M = DAG.getNode( in LowerRotate()
29060 M = DAG.getNode( in LowerRotate()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4243 return DAG.getNode( in lowerVECTOR_REVERSE()
5687 return DAG.getNode( in combineGREVI_GORCI()
5900 !Op0.getNode()->hasOneUse()) in PerformDAGCombine()
6074 !Op0.getNode()->hasOneUse()) in PerformDAGCombine()
6132 return DAG.getNode( in PerformDAGCombine()
6154 return DAG.getNode( in PerformDAGCombine()
7953 SDValue SplitF64 = DAG.getNode( in LowerCall()
7964 if (!StackPtr.getNode()) in LowerCall()
8045 if (!StackPtr.getNode()) in LowerCall()
8119 if (Glue.getNode()) in LowerCall()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp660 if (!IfClr.getNode()) { in performORCombine()
697 if (!IfClr.getNode()) in performORCombine()
700 assert(Cond.getNode() && IfSet.getNode()); in performORCombine()
805 return DAG.getNode(ISD::SHL, DL, VT, X, in genConstMult()
1056 if (Val.getNode()) { in PerformDAGCombine()
1339 if (In64.getNode()) in lowerDSPIntr()
1483 Exp2Imm = DAG.getNode( in lowerMSABinaryBitImmIntr()
1490 if (!Exp2Imm.getNode()) { in lowerMSABinaryBitImmIntr()
1618 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1893 return DAG.getNode( in lowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp282 if (Flag.getNode()) in LowerReturn_32()
361 if (Flag.getNode()) in LowerReturn_64()
969 if (InFlag.getNode()) in LowerCall_32()
1272 if (InGlue.getNode()) in LowerCall_64()
1314 if (!RV.getNode()) { in LowerCall_64()
1994 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); in makeAddress()
2125 return DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalTLSAddress()
2530 SDNode *Node = Op.getNode(); in LowerVAARG()
2620 SDValue Chain = DAG.getNode(SPISD::FLUSHW, in getFLUSHW()
2693 SDValue Ptr = DAG.getNode(ISD::ADD, in LowerRETURNADDR()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp163 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
181 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; in setRegister()
184 N = N.getDocument()->getNode(Val); in setRegister()
209 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val); in setNumUsedVgprs()
225 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val); in setNumUsedSgprs()
243 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val); in setFunctionScratchSize()
250 Node[".lds_size"] = MsgPackDoc.getNode(Val); in setFunctionLdsSize()
257 Node[".vgpr_count"] = MsgPackDoc.getNode(Val); in setFunctionNumUsedVgprs()
264 Node[".sgpr_count"] = MsgPackDoc.getNode(Val); in setFunctionNumUsedSgprs()
694 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true); in toString()
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