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Searched refs:constrainOperandRegClass (Results 1 – 15 of 15) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp305 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
327 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
328 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
354 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
1124 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1298 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); in SelectBranch()
1429 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1764 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
1765 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
H A DARMCallLowering.cpp476 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( in lowerCall()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h98 Register constrainOperandRegClass(const MachineFunction &MF,
117 Register constrainOperandRegClass(const MachineFunction &MF,
H A DInstructionSelectorImpl.h1071 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO); in executeMatchTable()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1916 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, in constrainOperandRegClass() function in FastISel
1947 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1968 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1969 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1991 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1992 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1993 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2017 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2039 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2082 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp156 constrainOperandRegClass(MF, *TRI, MRI, *TII, *RBI, II, II.getDesc(), in optimizeNZCVDefs()
H A DAArch64CallLowering.cpp1024 constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), in lowerTailCall()
1114 constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(), in lowerCall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1309 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1395 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
2049 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
2050 AddrReg = constrainOperandRegClass(II, AddrReg, 1); in emitStoreRelease()
2484 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2747 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
3239 CallReg = constrainOperandRegClass(II, CallReg, 0); in fastLowerCall()
4986 const unsigned AddrReg = constrainOperandRegClass( in selectAtomicCmpXchg()
4988 const unsigned DesiredReg = constrainOperandRegClass( in selectAtomicCmpXchg()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp48 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
93 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
130 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
167 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI); in constrainSelectedInstRegOperands()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h463 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp357 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
H A DX86FastISel.cpp226 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
650 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3965 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
3986 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
3987 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
3988 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
3989 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp1231 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerTailCall()
1348 MIB->getOperand(1).setReg(constrainOperandRegClass( in lowerCall()
H A DAMDGPUInstructionSelector.cpp493 SrcReg = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, I, in selectG_EXTRACT()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp2134 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2135 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()